prev_cmp_test.tan.qmsg

tranmiss data from kit to computer via com.

{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[7\] LEDR\[7\] 6.636 ns Longest " "Info: Longest tpd from source pin \"SW\[7\]\" to destination pin \"LEDR\[7\]\" is 6.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[7\] 1 PIN PIN_M2 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_M2; Fanout = 2; PIN Node = 'SW\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[7] } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.615 ns) + CELL(2.995 ns) 6.636 ns LEDR\[7\] 2 PIN PIN_U18 0 " "Info: 2: + IC(2.615 ns) + CELL(2.995 ns) = 6.636 ns; Loc. = PIN_U18; Fanout = 0; PIN Node = 'LEDR\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.610 ns" { SW[7] LEDR[7] } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.021 ns ( 60.59 % ) " "Info: Total cell delay = 4.021 ns ( 60.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.615 ns ( 39.41 % ) " "Info: Total interconnect delay = 2.615 ns ( 39.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.636 ns" { SW[7] LEDR[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.636 ns" { SW[7] {} SW[7]~combout {} LEDR[7] {} } { 0.000ns 0.000ns 2.615ns } { 0.000ns 1.026ns 2.995ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "UART_TX:TXD_BLOCK\|SENT_DATA\[2\] SW\[2\] CLOCK_50 0.693 ns register " "Info: th for register \"UART_TX:TXD_BLOCK\|SENT_DATA\[2\]\" (data pin = \"SW\[2\]\", clock pin = \"CLOCK_50\") is 0.693 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.867 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 22 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 22; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.602 ns) 2.867 ns UART_TX:TXD_BLOCK\|SENT_DATA\[2\] 3 REG LCFF_X44_Y12_N29 1 " "Info: 3: + IC(1.001 ns) + CELL(0.602 ns) = 2.867 ns; Loc. = LCFF_X44_Y12_N29; Fanout = 1; REG Node = 'UART_TX:TXD_BLOCK\|SENT_DATA\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.603 ns" { CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_DATA[2] } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.78 % ) " "Info: Total cell delay = 1.628 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.239 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.239 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_DATA[2] {} } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.460 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.460 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.036 ns) 1.036 ns SW\[2\] 1 PIN PIN_M22 2 " "Info: 1: + IC(0.000 ns) + CELL(1.036 ns) = 1.036 ns; Loc. = PIN_M22; Fanout = 2; PIN Node = 'SW\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[2] } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.150 ns) + CELL(0.178 ns) 2.364 ns UART_TX:TXD_BLOCK\|SENT_DATA\[2\]~feeder 2 COMB LCCOMB_X44_Y12_N28 1 " "Info: 2: + IC(1.150 ns) + CELL(0.178 ns) = 2.364 ns; Loc. = LCCOMB_X44_Y12_N28; Fanout = 1; COMB Node = 'UART_TX:TXD_BLOCK\|SENT_DATA\[2\]~feeder'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.328 ns" { SW[2] UART_TX:TXD_BLOCK|SENT_DATA[2]~feeder } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.460 ns UART_TX:TXD_BLOCK\|SENT_DATA\[2\] 3 REG LCFF_X44_Y12_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 2.460 ns; Loc. = LCFF_X44_Y12_N29; Fanout = 1; REG Node = 'UART_TX:TXD_BLOCK\|SENT_DATA\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { UART_TX:TXD_BLOCK|SENT_DATA[2]~feeder UART_TX:TXD_BLOCK|SENT_DATA[2] } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 53.25 % ) " "Info: Total cell delay = 1.310 ns ( 53.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.150 ns ( 46.75 % ) " "Info: Total interconnect delay = 1.150 ns ( 46.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.460 ns" { SW[2] UART_TX:TXD_BLOCK|SENT_DATA[2]~feeder UART_TX:TXD_BLOCK|SENT_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.460 ns" { SW[2] {} SW[2]~combout {} UART_TX:TXD_BLOCK|SENT_DATA[2]~feeder {} UART_TX:TXD_BLOCK|SENT_DATA[2] {} } { 0.000ns 0.000ns 1.150ns 0.000ns } { 0.000ns 1.036ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_DATA[2] {} } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.460 ns" { SW[2] UART_TX:TXD_BLOCK|SENT_DATA[2]~feeder UART_TX:TXD_BLOCK|SENT_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.460 ns" { SW[2] {} SW[2]~combout {} UART_TX:TXD_BLOCK|SENT_DATA[2]~feeder {} UART_TX:TXD_BLOCK|SENT_DATA[2] {} } { 0.000ns 0.000ns 1.150ns 0.000ns } { 0.000ns 1.036ns 0.178ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Peak virtual memory: 145 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 21 15:25:12 2008 " "Info: Processing ended: Tue Oct 21 15:25:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}