prev_cmp_test.tan.qmsg

tranmiss data from kit to computer via com.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "UART_TX:TXD_BLOCK\|BAUD_TICK " "Info: Detected ripple clock \"UART_TX:TXD_BLOCK\|BAUD_TICK\" as buffer" {  } { { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 25 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_TX:TXD_BLOCK\|BAUD_TICK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register UART_TX:TXD_BLOCK\|SENT_ENABLE register UART_TX:TXD_BLOCK\|BAUD_TICK 244.44 MHz 4.091 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 244.44 MHz between source register \"UART_TX:TXD_BLOCK\|SENT_ENABLE\" and destination register \"UART_TX:TXD_BLOCK\|BAUD_TICK\" (period= 4.091 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.020 ns + Longest register register " "Info: + Longest register to register delay is 3.020 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART_TX:TXD_BLOCK\|SENT_ENABLE 1 REG LCFF_X44_Y11_N1 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y11_N1; Fanout = 17; REG Node = 'UART_TX:TXD_BLOCK\|SENT_ENABLE'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_TX:TXD_BLOCK|SENT_ENABLE } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.262 ns) + CELL(0.758 ns) 3.020 ns UART_TX:TXD_BLOCK\|BAUD_TICK 2 REG LCFF_X1_Y13_N1 2 " "Info: 2: + IC(2.262 ns) + CELL(0.758 ns) = 3.020 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'UART_TX:TXD_BLOCK\|BAUD_TICK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.020 ns" { UART_TX:TXD_BLOCK|SENT_ENABLE UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.758 ns ( 25.10 % ) " "Info: Total cell delay = 0.758 ns ( 25.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.262 ns ( 74.90 % ) " "Info: Total interconnect delay = 2.262 ns ( 74.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.020 ns" { UART_TX:TXD_BLOCK|SENT_ENABLE UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.020 ns" { UART_TX:TXD_BLOCK|SENT_ENABLE {} UART_TX:TXD_BLOCK|BAUD_TICK {} } { 0.000ns 2.262ns } { 0.000ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.832 ns - Smallest " "Info: - Smallest clock skew is -0.832 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.032 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.602 ns) 2.032 ns UART_TX:TXD_BLOCK\|BAUD_TICK 2 REG LCFF_X1_Y13_N1 2 " "Info: 2: + IC(0.404 ns) + CELL(0.602 ns) = 2.032 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'UART_TX:TXD_BLOCK\|BAUD_TICK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.006 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 80.12 % ) " "Info: Total cell delay = 1.628 ns ( 80.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.404 ns ( 19.88 % ) " "Info: Total interconnect delay = 0.404 ns ( 19.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.032 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_TX:TXD_BLOCK|BAUD_TICK {} } { 0.000ns 0.000ns 0.404ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.864 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 22 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 22; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 2.864 ns UART_TX:TXD_BLOCK\|SENT_ENABLE 3 REG LCFF_X44_Y11_N1 17 " "Info: 3: + IC(0.998 ns) + CELL(0.602 ns) = 2.864 ns; Loc. = LCFF_X44_Y11_N1; Fanout = 17; REG Node = 'UART_TX:TXD_BLOCK\|SENT_ENABLE'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_ENABLE } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.84 % ) " "Info: Total cell delay = 1.628 ns ( 56.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.236 ns ( 43.16 % ) " "Info: Total interconnect delay = 1.236 ns ( 43.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_ENABLE } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_ENABLE {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.032 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_TX:TXD_BLOCK|BAUD_TICK {} } { 0.000ns 0.000ns 0.404ns } { 0.000ns 1.026ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_ENABLE } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_ENABLE {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.020 ns" { UART_TX:TXD_BLOCK|SENT_ENABLE UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.020 ns" { UART_TX:TXD_BLOCK|SENT_ENABLE {} UART_TX:TXD_BLOCK|BAUD_TICK {} } { 0.000ns 2.262ns } { 0.000ns 0.758ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.032 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.032 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_TX:TXD_BLOCK|BAUD_TICK {} } { 0.000ns 0.000ns 0.404ns } { 0.000ns 1.026ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_ENABLE } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_ENABLE {} } { 0.000ns 0.000ns 0.238ns 0.998ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "UART_TX:TXD_BLOCK\|SENT_DATA\[0\] SW\[9\] CLOCK_50 2.416 ns register " "Info: tsu for register \"UART_TX:TXD_BLOCK\|SENT_DATA\[0\]\" (data pin = \"SW\[9\]\", clock pin = \"CLOCK_50\") is 2.416 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.321 ns + Longest pin register " "Info: + Longest pin to register delay is 5.321 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns SW\[9\] 1 PIN PIN_L2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L2; Fanout = 3; PIN Node = 'SW\[9\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.152 ns) + CELL(0.545 ns) 3.723 ns UART_TX:TXD_BLOCK\|SENT_DATA\[7\]~110 2 COMB LCCOMB_X44_Y11_N24 9 " "Info: 2: + IC(2.152 ns) + CELL(0.545 ns) = 3.723 ns; Loc. = LCCOMB_X44_Y11_N24; Fanout = 9; COMB Node = 'UART_TX:TXD_BLOCK\|SENT_DATA\[7\]~110'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.697 ns" { SW[9] UART_TX:TXD_BLOCK|SENT_DATA[7]~110 } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.758 ns) 5.321 ns UART_TX:TXD_BLOCK\|SENT_DATA\[0\] 3 REG LCFF_X44_Y12_N23 1 " "Info: 3: + IC(0.840 ns) + CELL(0.758 ns) = 5.321 ns; Loc. = LCFF_X44_Y12_N23; Fanout = 1; REG Node = 'UART_TX:TXD_BLOCK\|SENT_DATA\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.598 ns" { UART_TX:TXD_BLOCK|SENT_DATA[7]~110 UART_TX:TXD_BLOCK|SENT_DATA[0] } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.329 ns ( 43.77 % ) " "Info: Total cell delay = 2.329 ns ( 43.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.992 ns ( 56.23 % ) " "Info: Total interconnect delay = 2.992 ns ( 56.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.321 ns" { SW[9] UART_TX:TXD_BLOCK|SENT_DATA[7]~110 UART_TX:TXD_BLOCK|SENT_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.321 ns" { SW[9] {} SW[9]~combout {} UART_TX:TXD_BLOCK|SENT_DATA[7]~110 {} UART_TX:TXD_BLOCK|SENT_DATA[0] {} } { 0.000ns 0.000ns 2.152ns 0.840ns } { 0.000ns 1.026ns 0.545ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.867 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 22 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 22; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.602 ns) 2.867 ns UART_TX:TXD_BLOCK\|SENT_DATA\[0\] 3 REG LCFF_X44_Y12_N23 1 " "Info: 3: + IC(1.001 ns) + CELL(0.602 ns) = 2.867 ns; Loc. = LCFF_X44_Y12_N23; Fanout = 1; REG Node = 'UART_TX:TXD_BLOCK\|SENT_DATA\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.603 ns" { CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_DATA[0] } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.78 % ) " "Info: Total cell delay = 1.628 ns ( 56.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.239 ns ( 43.22 % ) " "Info: Total interconnect delay = 1.239 ns ( 43.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_DATA[0] {} } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.321 ns" { SW[9] UART_TX:TXD_BLOCK|SENT_DATA[7]~110 UART_TX:TXD_BLOCK|SENT_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.321 ns" { SW[9] {} SW[9]~combout {} UART_TX:TXD_BLOCK|SENT_DATA[7]~110 {} UART_TX:TXD_BLOCK|SENT_DATA[0] {} } { 0.000ns 0.000ns 2.152ns 0.840ns } { 0.000ns 1.026ns 0.545ns 0.758ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.867 ns" { CLOCK_50 CLOCK_50~clkctrl UART_TX:TXD_BLOCK|SENT_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.867 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_TX:TXD_BLOCK|SENT_DATA[0] {} } { 0.000ns 0.000ns 0.238ns 1.001ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 UART_TXD UART_TX:TXD_BLOCK\|TXD 10.627 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"UART_TXD\" through register \"UART_TX:TXD_BLOCK\|TXD\" is 10.627 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 4.619 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 4.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 2 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.404 ns) + CELL(0.879 ns) 2.309 ns UART_TX:TXD_BLOCK\|BAUD_TICK 2 REG LCFF_X1_Y13_N1 2 " "Info: 2: + IC(0.404 ns) + CELL(0.879 ns) = 2.309 ns; Loc. = LCFF_X1_Y13_N1; Fanout = 2; REG Node = 'UART_TX:TXD_BLOCK\|BAUD_TICK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.000 ns) 3.019 ns UART_TX:TXD_BLOCK\|BAUD_TICK~clkctrl 3 COMB CLKCTRL_G0 12 " "Info: 3: + IC(0.710 ns) + CELL(0.000 ns) = 3.019 ns; Loc. = CLKCTRL_G0; Fanout = 12; COMB Node = 'UART_TX:TXD_BLOCK\|BAUD_TICK~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.710 ns" { UART_TX:TXD_BLOCK|BAUD_TICK UART_TX:TXD_BLOCK|BAUD_TICK~clkctrl } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 4.619 ns UART_TX:TXD_BLOCK\|TXD 4 REG LCFF_X44_Y11_N5 1 " "Info: 4: + IC(0.998 ns) + CELL(0.602 ns) = 4.619 ns; Loc. = LCFF_X44_Y11_N5; Fanout = 1; REG Node = 'UART_TX:TXD_BLOCK\|TXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { UART_TX:TXD_BLOCK|BAUD_TICK~clkctrl UART_TX:TXD_BLOCK|TXD } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 54.28 % ) " "Info: Total cell delay = 2.507 ns ( 54.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.112 ns ( 45.72 % ) " "Info: Total interconnect delay = 2.112 ns ( 45.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.619 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK UART_TX:TXD_BLOCK|BAUD_TICK~clkctrl UART_TX:TXD_BLOCK|TXD } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.619 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_TX:TXD_BLOCK|BAUD_TICK {} UART_TX:TXD_BLOCK|BAUD_TICK~clkctrl {} UART_TX:TXD_BLOCK|TXD {} } { 0.000ns 0.000ns 0.404ns 0.710ns 0.998ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.731 ns + Longest register pin " "Info: + Longest register to pin delay is 5.731 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART_TX:TXD_BLOCK\|TXD 1 REG LCFF_X44_Y11_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y11_N5; Fanout = 1; REG Node = 'UART_TX:TXD_BLOCK\|TXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_TX:TXD_BLOCK|TXD } "NODE_NAME" } } { "UART_TX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/UART_TX.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.755 ns) + CELL(2.976 ns) 5.731 ns UART_TXD 2 PIN PIN_G12 0 " "Info: 2: + IC(2.755 ns) + CELL(2.976 ns) = 5.731 ns; Loc. = PIN_G12; Fanout = 0; PIN Node = 'UART_TXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.731 ns" { UART_TX:TXD_BLOCK|TXD UART_TXD } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_TX/TEST.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.976 ns ( 51.93 % ) " "Info: Total cell delay = 2.976 ns ( 51.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.755 ns ( 48.07 % ) " "Info: Total interconnect delay = 2.755 ns ( 48.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.731 ns" { UART_TX:TXD_BLOCK|TXD UART_TXD } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.731 ns" { UART_TX:TXD_BLOCK|TXD {} UART_TXD {} } { 0.000ns 2.755ns } { 0.000ns 2.976ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.619 ns" { CLOCK_50 UART_TX:TXD_BLOCK|BAUD_TICK UART_TX:TXD_BLOCK|BAUD_TICK~clkctrl UART_TX:TXD_BLOCK|TXD } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.619 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_TX:TXD_BLOCK|BAUD_TICK {} UART_TX:TXD_BLOCK|BAUD_TICK~clkctrl {} UART_TX:TXD_BLOCK|TXD {} } { 0.000ns 0.000ns 0.404ns 0.710ns 0.998ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.731 ns" { UART_TX:TXD_BLOCK|TXD UART_TXD } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.731 ns" { UART_TX:TXD_BLOCK|TXD {} UART_TXD {} } { 0.000ns 2.755ns } { 0.000ns 2.976ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}