📄 test.tan.rpt
字号:
; N/A ; 372.86 MHz ( period = 2.682 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[9] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.443 ns ;
; N/A ; 372.86 MHz ( period = 2.682 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[9] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[8] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.443 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 374.39 MHz ( period = 2.671 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_DATA[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.435 ns ;
; N/A ; 375.80 MHz ( period = 2.661 ns ) ; UART_TX:TXD_BLOCK|STATE.bit6 ; UART_TX:TXD_BLOCK|TXD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.422 ns ;
; N/A ; 376.93 MHz ( period = 2.653 ns ) ; UART_TX:TXD_BLOCK|STATE.idle ; UART_TX:TXD_BLOCK|SENT_ENABLE ; CLOCK_50 ; CLOCK_50 ; None ; None ; 0.659 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[11] ; UART_TX:TXD_BLOCK|BAUD_TICK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.514 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[14] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[15] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[16] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[17] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[18] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[8] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.335 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[18] ; UART_TX:TXD_BLOCK|BAUD_TICK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.463 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|STATE.bit5 ; UART_TX:TXD_BLOCK|TXD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.177 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|STATE.bit2 ; UART_TX:TXD_BLOCK|TXD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.140 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[0] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[5] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[2] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[6] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[4] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[1] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_DATA[3] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.136 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[14] ; UART_TX:TXD_BLOCK|BAUD_TICK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.247 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[9] ; UART_TX:TXD_BLOCK|BAUD_TICK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.234 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|STATE.bit1 ; UART_TX:TXD_BLOCK|TXD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.008 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[14] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[15] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[16] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[17] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[18] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[11] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[9] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[8] ; CLOCK_50 ; CLOCK_50 ; None ; None ; 2.003 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; UART_TX:TXD_BLOCK|BAUD_TICK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.126 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|STATE.bit4 ; UART_TX:TXD_BLOCK|TXD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.890 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ENABLE ; UART_TX:TXD_BLOCK|SENT_ENABLE ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.805 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_DATA[0] ; UART_TX:TXD_BLOCK|TXD ; CLOCK_50 ; CLOCK_50 ; None ; None ; 3.525 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; UART_TX:TXD_BLOCK|BAUD_TICK ; CLOCK_50 ; CLOCK_50 ; None ; None ; 0.794 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX:TXD_BLOCK|SENT_ACTIVE ; UART_TX:TXD_BLOCK|SENT_ENABLE ; CLOCK_50 ; CLOCK_50 ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 380.08 MHz ( period = 2.631 ns ) ; UART_TX⌨️ 快捷键说明
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