test.tan.rpt

tranmiss data from kit to computer via com.

; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                               ; To                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 244.44 MHz ( period = 4.091 ns )                    ; UART_TX:TXD_BLOCK|SENT_ENABLE      ; UART_TX:TXD_BLOCK|BAUD_TICK        ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.020 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[14] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[15] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[16] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[17] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[18] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[11] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[9]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[10] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 267.09 MHz ( period = 3.744 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[8]  ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.505 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[13] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[14] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[12] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[15] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[16] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[17] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[18] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;
; N/A                                     ; 281.93 MHz ( period = 3.547 ns )                    ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[7]  ; UART_TX:TXD_BLOCK|BAUD_DIVIDER[11] ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.308 ns                ;