test.tan.qmsg

receiver data from computer via com-interface.

{ "Info" "ITDB_TSU_RESULT" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY UART_RXD CLOCK_50 4.584 ns register " "Info: tsu for register \"UART_RX:RXD_BLOCK\|RECEIVE_BUSY\" (data pin = \"UART_RXD\", clock pin = \"CLOCK_50\") is 4.584 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.963 ns + Longest pin register " "Info: + Longest pin to register delay is 7.963 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns UART_RXD 1 PIN PIN_F14 9 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F14; Fanout = 9; PIN Node = 'UART_RXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RXD } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.228 ns) + CELL(0.177 ns) 7.248 ns UART_RXD~_wirecell 2 COMB LCCOMB_X45_Y13_N14 1 " "Info: 2: + IC(6.228 ns) + CELL(0.177 ns) = 7.248 ns; Loc. = LCCOMB_X45_Y13_N14; Fanout = 1; COMB Node = 'UART_RXD~_wirecell'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.405 ns" { UART_RXD UART_RXD~_wirecell } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.413 ns) 7.963 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 3 REG LCFF_X45_Y13_N9 16 " "Info: 3: + IC(0.302 ns) + CELL(0.413 ns) = 7.963 ns; Loc. = LCFF_X45_Y13_N9; Fanout = 16; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.715 ns" { UART_RXD~_wirecell UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.433 ns ( 18.00 % ) " "Info: Total cell delay = 1.433 ns ( 18.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.530 ns ( 82.00 % ) " "Info: Total interconnect delay = 6.530 ns ( 82.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.963 ns" { UART_RXD UART_RXD~_wirecell UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.963 ns" { UART_RXD {} UART_RXD~combout {} UART_RXD~_wirecell {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 6.228ns 0.302ns } { 0.000ns 0.843ns 0.177ns 0.413ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 3.341 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 3.341 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.713 ns) + CELL(0.602 ns) 3.341 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 2 REG LCFF_X45_Y13_N9 16 " "Info: 2: + IC(1.713 ns) + CELL(0.602 ns) = 3.341 ns; Loc. = LCFF_X45_Y13_N9; Fanout = 16; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.315 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 48.73 % ) " "Info: Total cell delay = 1.628 ns ( 48.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.713 ns ( 51.27 % ) " "Info: Total interconnect delay = 1.713 ns ( 51.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.341 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.341 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 1.713ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.963 ns" { UART_RXD UART_RXD~_wirecell UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.963 ns" { UART_RXD {} UART_RXD~combout {} UART_RXD~_wirecell {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 6.228ns 0.302ns } { 0.000ns 0.843ns 0.177ns 0.413ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.341 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.341 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 1.713ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LEDG\[5\] LEDG\[5\]~reg0 12.208 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LEDG\[5\]\" through register \"LEDG\[5\]~reg0\" is 12.208 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 7.309 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 7.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.713 ns) + CELL(0.879 ns) 3.618 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 2 REG LCFF_X45_Y13_N9 16 " "Info: 2: + IC(1.713 ns) + CELL(0.879 ns) = 3.618 ns; Loc. = LCFF_X45_Y13_N9; Fanout = 16; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.087 ns) + CELL(0.000 ns) 5.705 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY~clkctrl 3 COMB CLKCTRL_G1 8 " "Info: 3: + IC(2.087 ns) + CELL(0.000 ns) = 5.705 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.087 ns" { UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 7.309 ns LEDG\[5\]~reg0 4 REG LCFF_X45_Y12_N9 1 " "Info: 4: + IC(1.002 ns) + CELL(0.602 ns) = 7.309 ns; Loc. = LCFF_X45_Y12_N9; Fanout = 1; REG Node = 'LEDG\[5\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 34.30 % ) " "Info: Total cell delay = 2.507 ns ( 34.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.802 ns ( 65.70 % ) " "Info: Total interconnect delay = 4.802 ns ( 65.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.309 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.309 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[5]~reg0 {} } { 0.000ns 0.000ns 1.713ns 2.087ns 1.002ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.622 ns + Longest register pin " "Info: + Longest register to pin delay is 4.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LEDG\[5\]~reg0 1 REG LCFF_X45_Y12_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X45_Y12_N9; Fanout = 1; REG Node = 'LEDG\[5\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[5]~reg0 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.762 ns) + CELL(2.860 ns) 4.622 ns LEDG\[5\] 2 PIN PIN_W21 0 " "Info: 2: + IC(1.762 ns) + CELL(2.860 ns) = 4.622 ns; Loc. = PIN_W21; Fanout = 0; PIN Node = 'LEDG\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.622 ns" { LEDG[5]~reg0 LEDG[5] } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.860 ns ( 61.88 % ) " "Info: Total cell delay = 2.860 ns ( 61.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.762 ns ( 38.12 % ) " "Info: Total interconnect delay = 1.762 ns ( 38.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.622 ns" { LEDG[5]~reg0 LEDG[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.622 ns" { LEDG[5]~reg0 {} LEDG[5] {} } { 0.000ns 1.762ns } { 0.000ns 2.860ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.309 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.309 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[5]~reg0 {} } { 0.000ns 0.000ns 1.713ns 2.087ns 1.002ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.622 ns" { LEDG[5]~reg0 LEDG[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.622 ns" { LEDG[5]~reg0 {} LEDG[5] {} } { 0.000ns 1.762ns } { 0.000ns 2.860ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\] UART_RXD CLOCK_50 -0.141 ns register " "Info: th for register \"UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\]\" (data pin = \"UART_RXD\", clock pin = \"CLOCK_50\") is -0.141 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 7.260 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 7.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.150 ns) + CELL(0.879 ns) 4.055 ns UART_RX:RXD_BLOCK\|BAUD_TICK 2 REG LCFF_X25_Y8_N1 3 " "Info: 2: + IC(2.150 ns) + CELL(0.879 ns) = 4.055 ns; Loc. = LCFF_X25_Y8_N1; Fanout = 3; REG Node = 'UART_RX:RXD_BLOCK\|BAUD_TICK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.000 ns) 5.671 ns UART_RX:RXD_BLOCK\|BAUD_TICK~clkctrl 3 COMB CLKCTRL_G13 17 " "Info: 3: + IC(1.616 ns) + CELL(0.000 ns) = 5.671 ns; Loc. = CLKCTRL_G13; Fanout = 17; COMB Node = 'UART_RX:RXD_BLOCK\|BAUD_TICK~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.616 ns" { UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 7.260 ns UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\] 4 REG LCFF_X45_Y13_N19 2 " "Info: 4: + IC(0.987 ns) + CELL(0.602 ns) = 7.260 ns; Loc. = LCFF_X45_Y13_N19; Fanout = 2; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|RECEIVE_DATA[6] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 34.53 % ) " "Info: Total cell delay = 2.507 ns ( 34.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.753 ns ( 65.47 % ) " "Info: Total interconnect delay = 4.753 ns ( 65.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.260 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|RECEIVE_DATA[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.260 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|RECEIVE_DATA[6] {} } { 0.000ns 0.000ns 2.150ns 1.616ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.687 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.687 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns UART_RXD 1 PIN PIN_F14 9 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F14; Fanout = 9; PIN Node = 'UART_RXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RXD } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.227 ns) + CELL(0.521 ns) 7.591 ns UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\]~63 2 COMB LCCOMB_X45_Y13_N18 1 " "Info: 2: + IC(6.227 ns) + CELL(0.521 ns) = 7.591 ns; Loc. = LCCOMB_X45_Y13_N18; Fanout = 1; COMB Node = 'UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\]~63'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.748 ns" { UART_RXD UART_RX:RXD_BLOCK|RECEIVE_DATA[6]~63 } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 7.687 ns UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\] 3 REG LCFF_X45_Y13_N19 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 7.687 ns; Loc. = LCFF_X45_Y13_N19; Fanout = 2; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_DATA\[6\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { UART_RX:RXD_BLOCK|RECEIVE_DATA[6]~63 UART_RX:RXD_BLOCK|RECEIVE_DATA[6] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.460 ns ( 18.99 % ) " "Info: Total cell delay = 1.460 ns ( 18.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.227 ns ( 81.01 % ) " "Info: Total interconnect delay = 6.227 ns ( 81.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.687 ns" { UART_RXD UART_RX:RXD_BLOCK|RECEIVE_DATA[6]~63 UART_RX:RXD_BLOCK|RECEIVE_DATA[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.687 ns" { UART_RXD {} UART_RXD~combout {} UART_RX:RXD_BLOCK|RECEIVE_DATA[6]~63 {} UART_RX:RXD_BLOCK|RECEIVE_DATA[6] {} } { 0.000ns 0.000ns 6.227ns 0.000ns } { 0.000ns 0.843ns 0.521ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.260 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|RECEIVE_DATA[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.260 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|RECEIVE_DATA[6] {} } { 0.000ns 0.000ns 2.150ns 1.616ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.687 ns" { UART_RXD UART_RX:RXD_BLOCK|RECEIVE_DATA[6]~63 UART_RX:RXD_BLOCK|RECEIVE_DATA[6] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.687 ns" { UART_RXD {} UART_RXD~combout {} UART_RX:RXD_BLOCK|RECEIVE_DATA[6]~63 {} UART_RX:RXD_BLOCK|RECEIVE_DATA[6] {} } { 0.000ns 0.000ns 6.227ns 0.000ns } { 0.000ns 0.843ns 0.521ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Peak virtual memory: 145 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 21 16:04:15 2008 " "Info: Processing ended: Tue Oct 21 16:04:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}