test.tan.qmsg

receiver data from computer via com-interface.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "UART_RX:RXD_BLOCK\|BAUD_TICK " "Info: Detected ripple clock \"UART_RX:RXD_BLOCK\|BAUD_TICK\" as buffer" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_RX:RXD_BLOCK\|BAUD_TICK" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY " "Info: Detected ripple clock \"UART_RX:RXD_BLOCK\|RECEIVE_BUSY\" as buffer" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "UART_RX:RXD_BLOCK\|RECEIVE_BUSY" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register UART_RX:RXD_BLOCK\|STATE.idle register UART_RX:RXD_BLOCK\|RXD_DATA\[0\] 161.47 MHz 6.193 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 161.47 MHz between source register \"UART_RX:RXD_BLOCK\|STATE.idle\" and destination register \"UART_RX:RXD_BLOCK\|RXD_DATA\[0\]\" (period= 6.193 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.562 ns + Longest register register " "Info: + Longest register to register delay is 1.562 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART_RX:RXD_BLOCK\|STATE.idle 1 REG LCFF_X44_Y13_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y13_N19; Fanout = 4; REG Node = 'UART_RX:RXD_BLOCK\|STATE.idle'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|STATE.idle } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.367 ns) + CELL(0.177 ns) 0.544 ns UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~107 2 COMB LCCOMB_X44_Y13_N4 8 " "Info: 2: + IC(0.367 ns) + CELL(0.177 ns) = 0.544 ns; Loc. = LCCOMB_X44_Y13_N4; Fanout = 8; COMB Node = 'UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~107'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.544 ns" { UART_RX:RXD_BLOCK|STATE.idle UART_RX:RXD_BLOCK|RXD_DATA[0]~107 } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.758 ns) 1.562 ns UART_RX:RXD_BLOCK\|RXD_DATA\[0\] 3 REG LCFF_X44_Y13_N17 1 " "Info: 3: + IC(0.260 ns) + CELL(0.758 ns) = 1.562 ns; Loc. = LCFF_X44_Y13_N17; Fanout = 1; REG Node = 'UART_RX:RXD_BLOCK\|RXD_DATA\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { UART_RX:RXD_BLOCK|RXD_DATA[0]~107 UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.935 ns ( 59.86 % ) " "Info: Total cell delay = 0.935 ns ( 59.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.627 ns ( 40.14 % ) " "Info: Total interconnect delay = 0.627 ns ( 40.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { UART_RX:RXD_BLOCK|STATE.idle UART_RX:RXD_BLOCK|RXD_DATA[0]~107 UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.562 ns" { UART_RX:RXD_BLOCK|STATE.idle {} UART_RX:RXD_BLOCK|RXD_DATA[0]~107 {} UART_RX:RXD_BLOCK|RXD_DATA[0] {} } { 0.000ns 0.367ns 0.260ns } { 0.000ns 0.177ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.392 ns - Smallest " "Info: - Smallest clock skew is -4.392 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.868 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns UART_RX:RXD_BLOCK\|RXD_DATA\[0\] 3 REG LCFF_X44_Y13_N17 1 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X44_Y13_N17; Fanout = 1; REG Node = 'UART_RX:RXD_BLOCK\|RXD_DATA\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { CLOCK_50 CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_RX:RXD_BLOCK|RXD_DATA[0] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 7.260 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 7.260 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.150 ns) + CELL(0.879 ns) 4.055 ns UART_RX:RXD_BLOCK\|BAUD_TICK 2 REG LCFF_X25_Y8_N1 3 " "Info: 2: + IC(2.150 ns) + CELL(0.879 ns) = 4.055 ns; Loc. = LCFF_X25_Y8_N1; Fanout = 3; REG Node = 'UART_RX:RXD_BLOCK\|BAUD_TICK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.029 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.616 ns) + CELL(0.000 ns) 5.671 ns UART_RX:RXD_BLOCK\|BAUD_TICK~clkctrl 3 COMB CLKCTRL_G13 17 " "Info: 3: + IC(1.616 ns) + CELL(0.000 ns) = 5.671 ns; Loc. = CLKCTRL_G13; Fanout = 17; COMB Node = 'UART_RX:RXD_BLOCK\|BAUD_TICK~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.616 ns" { UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.987 ns) + CELL(0.602 ns) 7.260 ns UART_RX:RXD_BLOCK\|STATE.idle 4 REG LCFF_X44_Y13_N19 4 " "Info: 4: + IC(0.987 ns) + CELL(0.602 ns) = 7.260 ns; Loc. = LCFF_X44_Y13_N19; Fanout = 4; REG Node = 'UART_RX:RXD_BLOCK\|STATE.idle'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|STATE.idle } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 34.53 % ) " "Info: Total cell delay = 2.507 ns ( 34.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.753 ns ( 65.47 % ) " "Info: Total interconnect delay = 4.753 ns ( 65.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.260 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|STATE.idle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.260 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|STATE.idle {} } { 0.000ns 0.000ns 2.150ns 1.616ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { CLOCK_50 CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_RX:RXD_BLOCK|RXD_DATA[0] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.260 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|STATE.idle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.260 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|STATE.idle {} } { 0.000ns 0.000ns 2.150ns 1.616ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.562 ns" { UART_RX:RXD_BLOCK|STATE.idle UART_RX:RXD_BLOCK|RXD_DATA[0]~107 UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.562 ns" { UART_RX:RXD_BLOCK|STATE.idle {} UART_RX:RXD_BLOCK|RXD_DATA[0]~107 {} UART_RX:RXD_BLOCK|RXD_DATA[0] {} } { 0.000ns 0.367ns 0.260ns } { 0.000ns 0.177ns 0.758ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { CLOCK_50 CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_RX:RXD_BLOCK|RXD_DATA[0] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.260 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|STATE.idle } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.260 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|STATE.idle {} } { 0.000ns 0.000ns 2.150ns 1.616ns 0.987ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLOCK_50 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"CLOCK_50\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "UART_RX:RXD_BLOCK\|RXD_DATA\[5\] LEDG\[5\]~reg0 CLOCK_50 3.268 ns " "Info: Found hold time violation between source  pin or register \"UART_RX:RXD_BLOCK\|RXD_DATA\[5\]\" and destination pin or register \"LEDG\[5\]~reg0\" for clock \"CLOCK_50\" (Hold time is 3.268 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.441 ns + Largest " "Info: + Largest clock skew is 4.441 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 7.309 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 7.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.713 ns) + CELL(0.879 ns) 3.618 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 2 REG LCFF_X45_Y13_N9 16 " "Info: 2: + IC(1.713 ns) + CELL(0.879 ns) = 3.618 ns; Loc. = LCFF_X45_Y13_N9; Fanout = 16; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.087 ns) + CELL(0.000 ns) 5.705 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY~clkctrl 3 COMB CLKCTRL_G1 8 " "Info: 3: + IC(2.087 ns) + CELL(0.000 ns) = 5.705 ns; Loc. = CLKCTRL_G1; Fanout = 8; COMB Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.087 ns" { UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 7.309 ns LEDG\[5\]~reg0 4 REG LCFF_X45_Y12_N9 1 " "Info: 4: + IC(1.002 ns) + CELL(0.602 ns) = 7.309 ns; Loc. = LCFF_X45_Y12_N9; Fanout = 1; REG Node = 'LEDG\[5\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 34.30 % ) " "Info: Total cell delay = 2.507 ns ( 34.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.802 ns ( 65.70 % ) " "Info: Total interconnect delay = 4.802 ns ( 65.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.309 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.309 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[5]~reg0 {} } { 0.000ns 0.000ns 1.713ns 2.087ns 1.002ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.868 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to source register is 2.868 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.238 ns) + CELL(0.000 ns) 1.264 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 20 " "Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.264 ns; Loc. = CLKCTRL_G2; Fanout = 20; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.238 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.602 ns) 2.868 ns UART_RX:RXD_BLOCK\|RXD_DATA\[5\] 3 REG LCFF_X44_Y13_N3 1 " "Info: 3: + IC(1.002 ns) + CELL(0.602 ns) = 2.868 ns; Loc. = LCFF_X44_Y13_N3; Fanout = 1; REG Node = 'UART_RX:RXD_BLOCK\|RXD_DATA\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.604 ns" { CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[5] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 56.76 % ) " "Info: Total cell delay = 1.628 ns ( 56.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.240 ns ( 43.24 % ) " "Info: Total interconnect delay = 1.240 ns ( 43.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { CLOCK_50 CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_RX:RXD_BLOCK|RXD_DATA[5] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.309 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.309 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[5]~reg0 {} } { 0.000ns 0.000ns 1.713ns 2.087ns 1.002ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { CLOCK_50 CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_RX:RXD_BLOCK|RXD_DATA[5] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns - " "Info: - Micro clock to output delay of source is 0.277 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.182 ns - Shortest register register " "Info: - Shortest register to register delay is 1.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns UART_RX:RXD_BLOCK\|RXD_DATA\[5\] 1 REG LCFF_X44_Y13_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X44_Y13_N3; Fanout = 1; REG Node = 'UART_RX:RXD_BLOCK\|RXD_DATA\[5\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RXD_DATA[5] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.178 ns) 1.086 ns LEDG\[5\]~reg0feeder 2 COMB LCCOMB_X45_Y12_N8 1 " "Info: 2: + IC(0.908 ns) + CELL(0.178 ns) = 1.086 ns; Loc. = LCCOMB_X45_Y12_N8; Fanout = 1; COMB Node = 'LEDG\[5\]~reg0feeder'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.086 ns" { UART_RX:RXD_BLOCK|RXD_DATA[5] LEDG[5]~reg0feeder } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.182 ns LEDG\[5\]~reg0 3 REG LCFF_X45_Y12_N9 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 1.182 ns; Loc. = LCFF_X45_Y12_N9; Fanout = 1; REG Node = 'LEDG\[5\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LEDG[5]~reg0feeder LEDG[5]~reg0 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.274 ns ( 23.18 % ) " "Info: Total cell delay = 0.274 ns ( 23.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.908 ns ( 76.82 % ) " "Info: Total interconnect delay = 0.908 ns ( 76.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.182 ns" { UART_RX:RXD_BLOCK|RXD_DATA[5] LEDG[5]~reg0feeder LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.182 ns" { UART_RX:RXD_BLOCK|RXD_DATA[5] {} LEDG[5]~reg0feeder {} LEDG[5]~reg0 {} } { 0.000ns 0.908ns 0.000ns } { 0.000ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.309 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.309 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[5]~reg0 {} } { 0.000ns 0.000ns 1.713ns 2.087ns 1.002ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.868 ns" { CLOCK_50 CLOCK_50~clkctrl UART_RX:RXD_BLOCK|RXD_DATA[5] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.868 ns" { CLOCK_50 {} CLOCK_50~combout {} CLOCK_50~clkctrl {} UART_RX:RXD_BLOCK|RXD_DATA[5] {} } { 0.000ns 0.000ns 0.238ns 1.002ns } { 0.000ns 1.026ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.182 ns" { UART_RX:RXD_BLOCK|RXD_DATA[5] LEDG[5]~reg0feeder LEDG[5]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.182 ns" { UART_RX:RXD_BLOCK|RXD_DATA[5] {} LEDG[5]~reg0feeder {} LEDG[5]~reg0 {} } { 0.000ns 0.908ns 0.000ns } { 0.000ns 0.178ns 0.096ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}