prev_cmp_test.qmsg

receiver data from computer via com-interface.

{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Info: Device EP2C15AF484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Info: Device EP2C35F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Info: Device EP2C50F484C7 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Info: Pin ~ASDO~ is reserved at location C4" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Info: Pin ~nCSO~ is reserved at location C3" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Info: Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } }  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY " "Info: Destination node UART_RX:RXD_BLOCK\|RECEIVE_BUSY" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_TICK " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_TICK" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "UART_RX:RXD_BLOCK\|BAUD_TICK  " "Info: Automatically promoted node UART_RX:RXD_BLOCK\|BAUD_TICK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~107 " "Info: Destination node UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~107" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RXD_DATA[0]~107 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~108 " "Info: Destination node UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~108" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RXD_DATA[0]~108 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY  " "Info: Automatically promoted node UART_RX:RXD_BLOCK\|RECEIVE_BUSY " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY " "Info: Destination node UART_RX:RXD_BLOCK\|RECEIVE_BUSY" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[14\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[14\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[14] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[13\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[13\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[13] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[11\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[11\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[11] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[12\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[12\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[12] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[9\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[9\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[9] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[8\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[8\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[8] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[6\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[6\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[6] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[7\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[7\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[7] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[10\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[10\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[10] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCDAT " "Warning: Ignored I/O standard assignment to node \"AUD_ADCDAT\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCDAT" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_ADCLRCK " "Warning: Ignored I/O standard assignment to node \"AUD_ADCLRCK\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_BCLK " "Warning: Ignored I/O standard assignment to node \"AUD_BCLK\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACDAT " "Warning: Ignored I/O standard assignment to node \"AUD_DACDAT\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACDAT" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_DACLRCK " "Warning: Ignored I/O standard assignment to node \"AUD_DACLRCK\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "AUD_XCK " "Warning: Ignored I/O standard assignment to node \"AUD_XCK\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "AUD_XCK" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[0\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[0\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_24\[1\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_27\[1\] " "Warning: Ignored I/O standard assignment to node \"CLOCK_27\[1\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "EXT_CLOCK " "Warning: Ignored I/O standard assignment to node \"EXT_CLOCK\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "EXT_CLOCK" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[0\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[0\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[10\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[10\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[11\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[11\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[12\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[12\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[13\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[13\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[14\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[14\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[15\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[15\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[16\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[16\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "GPIO_0\[17\] " "Warning: Ignored I/O standard assignment to node \"GPIO_0\[17\]\"" {  } { { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0