prev_cmp_test.qmsg

receiver data from computer via com-interface.

{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2\[3\] TEST.vhd(16) " "Warning (10034): Output port \"HEX2\[3\]\" at TEST.vhd(16) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2\[4\] TEST.vhd(16) " "Warning (10034): Output port \"HEX2\[4\]\" at TEST.vhd(16) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2\[5\] TEST.vhd(16) " "Warning (10034): Output port \"HEX2\[5\]\" at TEST.vhd(16) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX2\[6\] TEST.vhd(16) " "Warning (10034): Output port \"HEX2\[6\]\" at TEST.vhd(16) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 16 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[0\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[0\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[1\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[1\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[2\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[2\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[3\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[3\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[4\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[4\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[5\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[5\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "HEX3\[6\] TEST.vhd(17) " "Warning (10034): Output port \"HEX3\[6\]\" at TEST.vhd(17) has no driver" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 17 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UART_RX UART_RX:RXD_BLOCK " "Info: Elaborating entity \"UART_RX\" for hierarchy \"UART_RX:RXD_BLOCK\"" {  } { { "TEST.vhd" "RXD_BLOCK" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "TEMP UART_RX.vhd(29) " "Warning (10036): Verilog HDL or VHDL warning at UART_RX.vhd(29): object \"TEMP\" assigned a value but never read" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 29 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[0\] data_in GND " "Warning (14130): Reduced register \"UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[0\]\" with stuck data_in port to stuck value GND" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[1\] data_in GND " "Warning (14130): Reduced register \"UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[1\]\" with stuck data_in port to stuck value GND" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[2\] data_in GND " "Warning (14130): Reduced register \"UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[2\]\" with stuck data_in port to stuck value GND" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[3\] data_in GND " "Warning (14130): Reduced register \"UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[3\]\" with stuck data_in port to stuck value GND" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0 0}