prev_cmp_test.tan.qmsg

receiver data from computer via com-interface.

{ "Info" "ITDB_TSU_RESULT" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY UART_RXD CLOCK_50 4.495 ns register " "Info: tsu for register \"UART_RX:RXD_BLOCK\|RECEIVE_BUSY\" (data pin = \"UART_RXD\", clock pin = \"CLOCK_50\") is 4.495 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.983 ns + Longest pin register " "Info: + Longest pin to register delay is 7.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns UART_RXD 1 PIN PIN_F14 9 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F14; Fanout = 9; PIN Node = 'UART_RXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RXD } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.248 ns) + CELL(0.177 ns) 7.268 ns UART_RXD~_wirecell 2 COMB LCCOMB_X23_Y17_N14 1 " "Info: 2: + IC(6.248 ns) + CELL(0.177 ns) = 7.268 ns; Loc. = LCCOMB_X23_Y17_N14; Fanout = 1; COMB Node = 'UART_RXD~_wirecell'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.425 ns" { UART_RXD UART_RXD~_wirecell } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.413 ns) 7.983 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 3 REG LCFF_X23_Y17_N9 18 " "Info: 3: + IC(0.302 ns) + CELL(0.413 ns) = 7.983 ns; Loc. = LCFF_X23_Y17_N9; Fanout = 18; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.715 ns" { UART_RXD~_wirecell UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.433 ns ( 17.95 % ) " "Info: Total cell delay = 1.433 ns ( 17.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.550 ns ( 82.05 % ) " "Info: Total interconnect delay = 6.550 ns ( 82.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.983 ns" { UART_RXD UART_RXD~_wirecell UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.983 ns" { UART_RXD {} UART_RXD~combout {} UART_RXD~_wirecell {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 6.248ns 0.302ns } { 0.000ns 0.843ns 0.177ns 0.413ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 3.450 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 3.450 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.822 ns) + CELL(0.602 ns) 3.450 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 2 REG LCFF_X23_Y17_N9 18 " "Info: 2: + IC(1.822 ns) + CELL(0.602 ns) = 3.450 ns; Loc. = LCFF_X23_Y17_N9; Fanout = 18; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.424 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.628 ns ( 47.19 % ) " "Info: Total cell delay = 1.628 ns ( 47.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.822 ns ( 52.81 % ) " "Info: Total interconnect delay = 1.822 ns ( 52.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.450 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.450 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 1.822ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.983 ns" { UART_RXD UART_RXD~_wirecell UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.983 ns" { UART_RXD {} UART_RXD~combout {} UART_RXD~_wirecell {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 6.248ns 0.302ns } { 0.000ns 0.843ns 0.177ns 0.413ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.450 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.450 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} } { 0.000ns 0.000ns 1.822ns } { 0.000ns 1.026ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 LEDG\[0\] LEDG\[0\]~reg0 14.368 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"LEDG\[0\]\" through register \"LEDG\[0\]~reg0\" is 14.368 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 7.638 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 7.638 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.822 ns) + CELL(0.879 ns) 3.727 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY 2 REG LCFF_X23_Y17_N9 18 " "Info: 2: + IC(1.822 ns) + CELL(0.879 ns) = 3.727 ns; Loc. = LCFF_X23_Y17_N9; Fanout = 18; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.701 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.337 ns) + CELL(0.000 ns) 6.064 ns UART_RX:RXD_BLOCK\|RECEIVE_BUSY~clkctrl 3 COMB CLKCTRL_G8 8 " "Info: 3: + IC(2.337 ns) + CELL(0.000 ns) = 6.064 ns; Loc. = CLKCTRL_G8; Fanout = 8; COMB Node = 'UART_RX:RXD_BLOCK\|RECEIVE_BUSY~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.337 ns" { UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.972 ns) + CELL(0.602 ns) 7.638 ns LEDG\[0\]~reg0 4 REG LCFF_X24_Y19_N17 1 " "Info: 4: + IC(0.972 ns) + CELL(0.602 ns) = 7.638 ns; Loc. = LCFF_X24_Y19_N17; Fanout = 1; REG Node = 'LEDG\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.574 ns" { UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[0]~reg0 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 32.82 % ) " "Info: Total cell delay = 2.507 ns ( 32.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.131 ns ( 67.18 % ) " "Info: Total interconnect delay = 5.131 ns ( 67.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.638 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.638 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[0]~reg0 {} } { 0.000ns 0.000ns 1.822ns 2.337ns 0.972ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.453 ns + Longest register pin " "Info: + Longest register to pin delay is 6.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LEDG\[0\]~reg0 1 REG LCFF_X24_Y19_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y19_N17; Fanout = 1; REG Node = 'LEDG\[0\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDG[0]~reg0 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.603 ns) + CELL(2.850 ns) 6.453 ns LEDG\[0\] 2 PIN PIN_U22 0 " "Info: 2: + IC(3.603 ns) + CELL(2.850 ns) = 6.453 ns; Loc. = PIN_U22; Fanout = 0; PIN Node = 'LEDG\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { LEDG[0]~reg0 LEDG[0] } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.850 ns ( 44.17 % ) " "Info: Total cell delay = 2.850 ns ( 44.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.603 ns ( 55.83 % ) " "Info: Total interconnect delay = 3.603 ns ( 55.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { LEDG[0]~reg0 LEDG[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.453 ns" { LEDG[0]~reg0 {} LEDG[0] {} } { 0.000ns 3.603ns } { 0.000ns 2.850ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.638 ns" { CLOCK_50 UART_RX:RXD_BLOCK|RECEIVE_BUSY UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl LEDG[0]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.638 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|RECEIVE_BUSY {} UART_RX:RXD_BLOCK|RECEIVE_BUSY~clkctrl {} LEDG[0]~reg0 {} } { 0.000ns 0.000ns 1.822ns 2.337ns 0.972ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { LEDG[0]~reg0 LEDG[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.453 ns" { LEDG[0]~reg0 {} LEDG[0] {} } { 0.000ns 3.603ns } { 0.000ns 2.850ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\] UART_RXD CLOCK_50 0.646 ns register " "Info: th for register \"UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\]\" (data pin = \"UART_RXD\", clock pin = \"CLOCK_50\") is 0.646 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 7.751 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 7.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.026 ns) 1.026 ns CLOCK_50 1 CLK PIN_L1 3 " "Info: 1: + IC(0.000 ns) + CELL(1.026 ns) = 1.026 ns; Loc. = PIN_L1; Fanout = 3; CLK Node = 'CLOCK_50'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.163 ns) + CELL(0.879 ns) 4.068 ns UART_RX:RXD_BLOCK\|BAUD_TICK 2 REG LCFF_X25_Y18_N17 3 " "Info: 2: + IC(2.163 ns) + CELL(0.879 ns) = 4.068 ns; Loc. = LCFF_X25_Y18_N17; Fanout = 3; REG Node = 'UART_RX:RXD_BLOCK\|BAUD_TICK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.042 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.000 ns) 6.176 ns UART_RX:RXD_BLOCK\|BAUD_TICK~clkctrl 3 COMB CLKCTRL_G14 17 " "Info: 3: + IC(2.108 ns) + CELL(0.000 ns) = 6.176 ns; Loc. = CLKCTRL_G14; Fanout = 17; COMB Node = 'UART_RX:RXD_BLOCK\|BAUD_TICK~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.108 ns" { UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.973 ns) + CELL(0.602 ns) 7.751 ns UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\] 4 REG LCFF_X22_Y17_N17 2 " "Info: 4: + IC(0.973 ns) + CELL(0.602 ns) = 7.751 ns; Loc. = LCFF_X22_Y17_N17; Fanout = 2; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.575 ns" { UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|RECEIVE_DATA[2] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.507 ns ( 32.34 % ) " "Info: Total cell delay = 2.507 ns ( 32.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.244 ns ( 67.66 % ) " "Info: Total interconnect delay = 5.244 ns ( 67.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.751 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|RECEIVE_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.751 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|RECEIVE_DATA[2] {} } { 0.000ns 0.000ns 2.163ns 2.108ns 0.973ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.391 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.391 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.843 ns) 0.843 ns UART_RXD 1 PIN PIN_F14 9 " "Info: 1: + IC(0.000 ns) + CELL(0.843 ns) = 0.843 ns; Loc. = PIN_F14; Fanout = 9; PIN Node = 'UART_RXD'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RXD } "NODE_NAME" } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.274 ns) + CELL(0.178 ns) 7.295 ns UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\]~59 2 COMB LCCOMB_X22_Y17_N16 1 " "Info: 2: + IC(6.274 ns) + CELL(0.178 ns) = 7.295 ns; Loc. = LCCOMB_X22_Y17_N16; Fanout = 1; COMB Node = 'UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\]~59'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.452 ns" { UART_RXD UART_RX:RXD_BLOCK|RECEIVE_DATA[2]~59 } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 7.391 ns UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\] 3 REG LCFF_X22_Y17_N17 2 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 7.391 ns; Loc. = LCFF_X22_Y17_N17; Fanout = 2; REG Node = 'UART_RX:RXD_BLOCK\|RECEIVE_DATA\[2\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { UART_RX:RXD_BLOCK|RECEIVE_DATA[2]~59 UART_RX:RXD_BLOCK|RECEIVE_DATA[2] } "NODE_NAME" } } { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.117 ns ( 15.11 % ) " "Info: Total cell delay = 1.117 ns ( 15.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.274 ns ( 84.89 % ) " "Info: Total interconnect delay = 6.274 ns ( 84.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.391 ns" { UART_RXD UART_RX:RXD_BLOCK|RECEIVE_DATA[2]~59 UART_RX:RXD_BLOCK|RECEIVE_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.391 ns" { UART_RXD {} UART_RXD~combout {} UART_RX:RXD_BLOCK|RECEIVE_DATA[2]~59 {} UART_RX:RXD_BLOCK|RECEIVE_DATA[2] {} } { 0.000ns 0.000ns 6.274ns 0.000ns } { 0.000ns 0.843ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.751 ns" { CLOCK_50 UART_RX:RXD_BLOCK|BAUD_TICK UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl UART_RX:RXD_BLOCK|RECEIVE_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.751 ns" { CLOCK_50 {} CLOCK_50~combout {} UART_RX:RXD_BLOCK|BAUD_TICK {} UART_RX:RXD_BLOCK|BAUD_TICK~clkctrl {} UART_RX:RXD_BLOCK|RECEIVE_DATA[2] {} } { 0.000ns 0.000ns 2.163ns 2.108ns 0.973ns } { 0.000ns 1.026ns 0.879ns 0.000ns 0.602ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.391 ns" { UART_RXD UART_RX:RXD_BLOCK|RECEIVE_DATA[2]~59 UART_RX:RXD_BLOCK|RECEIVE_DATA[2] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.391 ns" { UART_RXD {} UART_RXD~combout {} UART_RX:RXD_BLOCK|RECEIVE_DATA[2]~59 {} UART_RX:RXD_BLOCK|RECEIVE_DATA[2] {} } { 0.000ns 0.000ns 6.274ns 0.000ns } { 0.000ns 0.843ns 0.178ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Peak virtual memory: 145 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 21 16:03:04 2008 " "Info: Processing ended: Tue Oct 21 16:03:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}