test.fit.qmsg

receiver data from computer via com-interface.

{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY " "Info: Destination node UART_RX:RXD_BLOCK\|RECEIVE_BUSY" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_TICK " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_TICK" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/80/quartus/bin/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "TEST.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/TEST.vhd" 6 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "UART_RX:RXD_BLOCK\|BAUD_TICK  " "Info: Automatically promoted node UART_RX:RXD_BLOCK\|BAUD_TICK " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~107 " "Info: Destination node UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~107" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RXD_DATA[0]~107 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~108 " "Info: Destination node UART_RX:RXD_BLOCK\|RXD_DATA\[0\]~108" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 85 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RXD_DATA[0]~108 } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 24 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_TICK } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY  " "Info: Automatically promoted node UART_RX:RXD_BLOCK\|RECEIVE_BUSY " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Info: Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|RECEIVE_BUSY " "Info: Destination node UART_RX:RXD_BLOCK\|RECEIVE_BUSY" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[14\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[14\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[14] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[15\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[15\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[15] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[13\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[13\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[13] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[9\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[9\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[9] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[12\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[12\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[12] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[11\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[11\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[11] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[10\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[10\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[10] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[7\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[7\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[7] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[8\] " "Info: Destination node UART_RX:RXD_BLOCK\|BAUD_DIVIDER\[8\]" {  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 34 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|BAUD_DIVIDER[8] } "NODE_NAME" } }  } 0 0 "Destination node %1!s!" 0 0 "" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" {  } {  } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 0}  } {  } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 0}  } { { "UART_RX.vhd" "" { Text "D:/Term 9/VHDL/BIG EXAM VHDL/UART_RX/UART_RX.vhd" 28 -1 0 } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { UART_RX:RXD_BLOCK|RECEIVE_BUSY } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 0}