test.tan.rpt

receiver data from computer via com-interface.

; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLOCK_50        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLOCK_50'                                                                                                                                                                                                                                                             ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                               ; To                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[0]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[1]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[2]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[3]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[4]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[5]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[6]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 161.47 MHz ( period = 6.193 ns )                    ; UART_RX:RXD_BLOCK|STATE.idle       ; UART_RX:RXD_BLOCK|RXD_DATA[7]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 1.562 ns                ;
; N/A                                     ; 181.95 MHz ( period = 5.496 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[6]  ; UART_RX:RXD_BLOCK|RXD_DATA[6]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.865 ns                ;
; N/A                                     ; 182.22 MHz ( period = 5.488 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[7]  ; UART_RX:RXD_BLOCK|RXD_DATA[7]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.857 ns                ;
; N/A                                     ; 185.19 MHz ( period = 5.400 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[0]  ; UART_RX:RXD_BLOCK|RXD_DATA[0]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.769 ns                ;
; N/A                                     ; 190.01 MHz ( period = 5.263 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[4]  ; UART_RX:RXD_BLOCK|RXD_DATA[4]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.632 ns                ;
; N/A                                     ; 190.04 MHz ( period = 5.262 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[1]  ; UART_RX:RXD_BLOCK|RXD_DATA[1]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.631 ns                ;
; N/A                                     ; 190.08 MHz ( period = 5.261 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[3]  ; UART_RX:RXD_BLOCK|RXD_DATA[3]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.630 ns                ;
; N/A                                     ; 190.33 MHz ( period = 5.254 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[2]  ; UART_RX:RXD_BLOCK|RXD_DATA[2]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.623 ns                ;
; N/A                                     ; 190.40 MHz ( period = 5.252 ns )                    ; UART_RX:RXD_BLOCK|RECEIVE_DATA[5]  ; UART_RX:RXD_BLOCK|RXD_DATA[5]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 0.621 ns                ;
; N/A                                     ; 194.48 MHz ( period = 5.142 ns )                    ; UART_RX:RXD_BLOCK|BAUD_TICK        ; UART_RX:RXD_BLOCK|RXD_DATA[0]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.993 ns                ;
; N/A                                     ; 194.48 MHz ( period = 5.142 ns )                    ; UART_RX:RXD_BLOCK|BAUD_TICK        ; UART_RX:RXD_BLOCK|RXD_DATA[1]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.993 ns                ;
; N/A                                     ; 194.48 MHz ( period = 5.142 ns )                    ; UART_RX:RXD_BLOCK|BAUD_TICK        ; UART_RX:RXD_BLOCK|RXD_DATA[2]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.993 ns                ;
; N/A                                     ; 194.48 MHz ( period = 5.142 ns )                    ; UART_RX:RXD_BLOCK|BAUD_TICK        ; UART_RX:RXD_BLOCK|RXD_DATA[3]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.993 ns                ;
; N/A                                     ; 194.48 MHz ( period = 5.142 ns )                    ; UART_RX:RXD_BLOCK|BAUD_TICK        ; UART_RX:RXD_BLOCK|RXD_DATA[4]      ; CLOCK_50   ; CLOCK_50 ; None                        ; None                      ; 3.993 ns                ;