test.vhd

来自「receiver data from computer via com-inte」· VHDL 代码 · 共 81 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TEST IS
PORT(
		CLOCK_50	: IN STD_LOGIC;
		UART_RXD	: IN STD_LOGIC;
		SW			: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		KEY			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		
		UART_TXD	: OUT STD_LOGIC;
		LEDR		: OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
		LEDG		: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		HEX0		: OUT STD_LOGIC_VECTOR(0 TO 6);
		HEX1		: OUT STD_LOGIC_VECTOR(0 TO 6);
		HEX2		: OUT STD_LOGIC_VECTOR(0 TO 6);
		HEX3		: OUT STD_LOGIC_VECTOR(0 TO 6)
	);
END TEST;

ARCHITECTURE STRUCT OF TEST IS

COMPONENT UART_RX
GENERIC(
		SYNC_CLOCK 	: INTEGER := 50000000;
		BAUD_RATE	: INTEGER := 9600
	);
PORT(
		CLOCK			: IN STD_LOGIC;
		RXD				: IN STD_LOGIC;
		
		RXD_DATA_VALID	: OUT STD_LOGIC;
		RXD_DATA		: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;

SIGNAL RXD			: STD_LOGIC;
SIGNAL RXD_DATA		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL RXD_VALID	: STD_LOGIC;

BEGIN
	
	RXD_BLOCK: UART_RX
		GENERIC MAP(
			50000000,
			115200
			)
		PORT MAP(
			CLOCK			=> CLOCK_50,
			RXD				=> RXD,
			RXD_DATA		=> RXD_DATA,
			RXD_DATA_VALID	=> RXD_VALID
			);
	PROCESS(RXD_VALID)
	BEGIN
		IF (RXD_VALID'EVENT AND RXD_VALID = '1') THEN
			LEDG <= RXD_DATA;
		END IF;
	END PROCESS;
	
	RXD <= UART_RXD;
	
END STRUCT;