dsmlib.c

vxworks的源代码

    {"evmwhsmi",     _VOP(4, 1101),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhsmia",    _VOP(4, 1133),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhssf",     _VOP(4, 1095),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhssfa",    _VOP(4, 1127),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhumi",     _VOP(4, 1100),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhumia",    _VOP(4, 1132),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhusiaaw",  _VOP(4, 1348),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwhusianw",  _VOP(4, 1476),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwlumi",     _VOP(4, 1096),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwlumia",    _VOP(4, 1128),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwlumiaaw",  _VOP(4, 1352),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwlumianw",  _VOP(4, 1480),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwlusiaaw",  _VOP(4, 1344),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwlusianw",  _VOP(4, 1472),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmf",      _VOP(4, 1115),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmfa",     _VOP(4, 1147),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmfaa",    _VOP(4, 1371),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmfan",    _VOP(4, 1499),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmi",      _VOP(4, 1113),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmia",     _VOP(4, 1145),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmiaa",    _VOP(4, 1369),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwsmian",    _VOP(4, 1497),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwssf",      _VOP(4, 1107),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwssfa",     _VOP(4, 1139),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwssfaa",    _VOP(4, 1363),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwssfan",    _VOP(4, 1491),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwumi",      _VOP(4, 1112),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwumia",     _VOP(4, 1144),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwumiaa",    _VOP(4, 1368),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evmwumian",    _VOP(4, 1496),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evnand",       _VOP(4,  542),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evneg",        _VOP(4,  521),  _IFORM_EVX_3,  _IFLAG_E500_SPEC},
    {"evnor",        _VOP(4,  536),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evor",         _VOP(4,  535),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evorc",        _VOP(4,  539),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evrlw",        _VOP(4,  552),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evrlwi",       _VOP(4,  554),  _IFORM_EVX_5,  _IFLAG_E500_SPEC},
    {"evrndw",       _VOP(4,  524),  _IFORM_EVX_3,  _IFLAG_E500_SPEC},
    {"evslw",        _VOP(4,  548),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evslwi",       _VOP(4,  550),  _IFORM_EVX_5,  _IFLAG_E500_SPEC},
    {"evsplatfi",    _VOP(4,  555),  _IFORM_EVX_7,  _IFLAG_E500_SPEC},
    {"evsplati",     _VOP(4,  553),  _IFORM_EVX_7,  _IFLAG_E500_SPEC},
    {"evsrwis",      _VOP(4,  547),  _IFORM_EVX_5,  _IFLAG_E500_SPEC},
    {"evsrwiu",      _VOP(4,  546),  _IFORM_EVX_5,  _IFLAG_E500_SPEC},
    {"evsrws",       _VOP(4,  545),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evsrwu",       _VOP(4,  544),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evstdd",       _VOP(4,  801),  _IFORM_EVX_11, _IFLAG_E500_SPEC},
    {"evstddx",      _VOP(4,  800),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evstdh",       _VOP(4,  805),  _IFORM_EVX_9,  _IFLAG_E500_SPEC},
    {"evstdhx",      _VOP(4,  804),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evstdw",       _VOP(4,  803),  _IFORM_EVX_9,  _IFLAG_E500_SPEC},
    {"evstdwx",      _VOP(4,  802),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evstwhe",      _VOP(4,  817),  _IFORM_EVX_10, _IFLAG_E500_SPEC},
    {"evstwhex",     _VOP(4,  816),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evstwho",      _VOP(4,  821),  _IFORM_EVX_10, _IFLAG_E500_SPEC},
    {"evstwhox",     _VOP(4,  820),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evstwwe",      _VOP(4,  825),  _IFORM_EVX_10, _IFLAG_E500_SPEC},
    {"evstwwex",     _VOP(4,  824),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evstwwo",      _VOP(4,  829),  _IFORM_EVX_10, _IFLAG_E500_SPEC},
    {"evstwwox",     _VOP(4,  828),  _IFORM_EVX_8,  _IFLAG_E500_SPEC},
    {"evsubfsmiaaw", _VOP(4, 1227),  _IFORM_EVX_3,  _IFLAG_E500_SPEC},
    {"evsubfssiaaw", _VOP(4, 1219),  _IFORM_EVX_3,  _IFLAG_E500_SPEC},
    {"evsubfumiaaw", _VOP(4, 1226),  _IFORM_EVX_3,  _IFLAG_E500_SPEC},
    {"evsubfusiaaw", _VOP(4, 1218),  _IFORM_EVX_3,  _IFLAG_E500_SPEC},
    {"evsubfw",      _VOP(4,  516),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
    {"evsubifw",     _VOP(4,  518),  _IFORM_EVX_14, _IFLAG_E500_SPEC},
    {"evxor",        _VOP(4,  534),  _IFORM_EVX_1,  _IFLAG_E500_SPEC},
#endif /* HOST || (CPU==PPC85XX) */

    {"rlwimi",   _OP(20,    0),     _IFORM_M_1,     _IFLAG_RC},
    {"rlwinm",   _OP(21,    0),     _IFORM_M_1,     _IFLAG_RC},
    {"rlwnm",    _OP(23,    0),     _IFORM_M_2,     _IFLAG_RC}

    };    /* end of inst[] */

LOCAL SPR spr [] =
    {
    /* The following SPRs are generic to all PowerPC processors */

    {9,		"CTR"},  	/* count */
    {8,		"LR"},   	/* link */
    {287,	"PVR"},		/* processor version */
    {272,	"SPRG0"},	/* operating system use */
    {273,	"SPRG1"},	/* operating system use */
    {274,	"SPRG2"},	/* operating system use */
    {275,	"SPRG3"},	/* operating system use */
    {26,	"SRR0"},	/* save/restore */
    {27,	"SRR1"},	/* save/restore */
    {1,		"XER"},		/* integer exception */

    /*
     * The following SPRs are processor specific.  On the host,
     * create a separate array for each CPU or group of similar
     * CPU's.  On each target, include only its own definitions.
     */

#if	(defined(HOST) || (CPU == PPC403))
# if	defined(HOST)
    {NONE,	""}		/* END OF LIST */
    };
LOCAL SPR spr403 [] =
    {
# endif	/* HOST */
    {0x3d7,	"CDBCR"},
    {0x3f6,	"DAC1"},
    {0x3f7,	"DAC2"},
    {0x3f2,	"DBCR"},
    {0x3f0,	"DBSR"},
    {0x3fa,	"DCCR"},
    {0x3d5,	"DEAR"},
    {0x3d4,	"ESR"},
    {0x3d6,	"EVPR"},
    {0x3f4,	"IAC1"},
    {0x3f5,	"IAC2"},
    {0x3fb,	"ICCR"},
    {0x3d3,	"ICDBDR"},
    {0x3fc,	"PBL1"},
    {0x3fe,	"PBL2"},
    {0x3fd,	"PBU1"},
    {0x3ff,	"PBU2"},
    {0x3db,	"PIT"},
    {0x3de,	"SRR2"},
    {0x3df,	"SRR3"},
    {0x3dc,	"TBHI"},
    {0x3dd,	"TBLO"},
    {0x3da,	"TCR"},
    {0x3d8,	"TSR"},
#endif	/* HOST || PPC403 */

#if	(defined(HOST) || (CPU == PPC405) || (CPU == PPC405F))
# if	defined(HOST)
    {NONE,	""}		/* END OF LIST */
    };
LOCAL SPR spr405 [] =
    {
# endif	/* HOST */
    {0x3b3,	"CCR0"},
    {0x3f6,	"DAC1"},
    {0x3f7,	"DAC2"},
    {0x3f2,	"DBCR0"},
    {0x3bd,	"DBCR1"},
    {0x3f0,	"DBSR"},
    {0x3fa,	"DCCR"},
    {0x3ba,	"DCWR"},
    {0x3d5,	"DEAR"},
    {0x3b6,	"DVC1"},
    {0x3b7,	"DVC2"},
    {0x3d4,	"ESR"},
    {0x3d6,	"EVPR"},
    {0x3f4,	"IAC1"},
    {0x3f5,	"IAC2"},
    {0x3b4,	"IAC3"},
    {0x3b5,	"IAC4"},
    {0x3fb,	"ICCR"},
    {0x3d3,	"ICDBDR"},
    {0x008,	"LR"},
    {0x3b1,	"PID"},
    {0x3db,	"PIT"},
    {0x3b9,	"SGR"},
    {0x3bb,	"SLER"},
    {0x114,	"SPRG4"},
    {0x104,	"SPRG4_R"},
    {0x115,	"SPRG5"},
    {0x105,	"SPRG5_R"},
    {0x116,	"SPRG6"},
    {0x106,	"SPRG6_R"},
    {0x117,	"SPRG7"},
    {0x107,	"SPRG7_R"},
    {0x3de,	"SRR2"},
    {0x3df,	"SRR3"},
    {0x3bc,	"SU0R"},
    {0x10c,	"TBL"},
    {0x11c,	"TBL"},
    {0x10d,	"TBU"},
    {0x11d,	"TBU"},
    {0x3da,	"TCR"},
    {0x3d8,	"TSR"},
    {0x100,	"USPRG0"},
    {0x3b0,	"ZPR"},
#endif	/* HOST || PPC405 || PPC405F */

#if	(defined(HOST) || (CPU == PPC440))
# if	defined(HOST)
    {NONE,	""}		/* END OF LIST */
    };
LOCAL SPR spr440 [] =
    {
# endif	/* HOST */
    {0x3B3,	"CCR0"},	/* Core Configuration Register 0 */
    {0x03A,	"CSRR0"},	/* Critical Save/Restore Register 0 */
    {0x03B,	"CSRR1"},	/* Critical Save/Restore Register 1 */
    {0x13C,	"DAC1"},	/* Data Address Compare 1 */
    {0x13D,	"DAC2"},	/* Data Address Compare 2 */
    {0x134,	"DBCR0"},	/* Debug Control Register 0 */
    {0x135,	"DBCR1"},	/* Debug Control Register 1 */
    {0x136,	"DBCR2"},	/* Debug Control Register 2 */
    {0x3F3,	"DBDR"},	/* Debug Data Register */
    {0x130,	"DBSR"},	/* Debug Status Register */
    {0x39D,	"DCDBTRH"},	/* Data Cache Debug Tag Register High */
    {0x39C,	"DCDBTRL"},	/* Data Cache Debug Tag Register Low */
    {0x03D,	"DEAR"},	/* Data Exception Address Register */
    {0x016,	"DEC"},		/* Decrementer */
    {0x036,	"DECAR"},	/* Decrementer Auto-Reload */
    {0x390,	"DNV0"},	/* Data Cache Normal Victim 0 */
    {0x391,	"DNV1"},	/* Data Cache Normal Victim 1 */
    {0x392,	"DNV2"},	/* Data Cache Normal Victim 2 */
    {0x393,	"DNV3"},	/* Data Cache Normal Victim 3 */
    {0x394,	"DTV0"},	/* Data Cache Transient Victim 0 */
    {0x395,	"DTV1"},	/* Data Cache Transient Victim 1 */
    {0x396,	"DTV2"},	/* Data Cache Transient Victim 2 */
    {0x397,	"DTV3"},	/* Data Cache Transient Victim 3 */
    {0x13E,	"DVC1"},	/* Data Value Compare 1 */
    {0x13F,	"DVC2"},	/* Data Value Compare 2 */
    {0x398,	"DVLIM"},	/* Data Cache Victim Limit */
    {0x03E,	"ESR"},		/* Exception Syndrome Register */
    {0x138,	"IAC1"},	/* Instruction Address Compare 1 */
    {0x139,	"IAC2"},	/* Instruction Address Compare 2 */
    {0x13A,	"IAC3"},	/* Instruction Address Compare 3 */
    {0x13B,	"IAC4"},	/* Instruction Address Compare 4 */
    {0x3D3,	"ICDBDR"},	/* Instruction Cache Debug Data Register */
    {0x39F,	"ICDBTRH"},	/* Instruction Cache Debug Tag Register High */
    {0x39E,	"ICDBTRL"},	/* Instruction Cache Debug Tag Register Low */
    {0x370,	"INV0"},	/* Instruction Cache Normal Victim 0 */
    {0x371,	"INV1"},	/* Instruction Cache Normal Victim 1 */
    {0x372,	"INV2"},	/* Instruction Cache Normal Victim 2 */
    {0x373,	"INV3"},	/* Instruction Cache Normal Victim 3 */
    {0x374,	"ITV0"},	/* Instruction Cache Transient Victim 0 */
    {0x375,	"ITV1"},	/* Instruction Cache Transient Victim 1 */
    {0x376,	"ITV2"},	/* Instruction Cache Transient Victim 2 */
    {0x377,	"ITV3"},	/* Instruction Cache Transient Victim 3 */
    {0x399,	"IVLIM"},	/* Instruction Cache Victim Limit */
    {0x190,	"IVOR0"},	/* Critical Input */
    {0x191,	"IVOR1"},	/* Machine C