cacher4kalib.s

vxworks的源代码

	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR4kDCacheSize
	blez	a2, 99f
	lw	a3,cacheR4kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheR4kDCFlushInvalidateAll

/*******************************************************************************
*
* cacheR4kDCFlush - flush R4000 data cache locations
*
* RETURNS: N/A
*

* void cacheR4kDCFlushInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR4kDCFlushInvalidate
FUNC_LABEL(cacheR4kDCFlushInvalidate)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR4kSCacheSize
	blez	a2,1f
	lw	a3,cacheR4kSCacheLineSize
	move	a1,a2
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR4kDCacheSize
	blez	a2, 99f
	lw	a3,cacheR4kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
99:	j	ra
	.end	cacheR4kDCFlushInvalidate


/*******************************************************************************
*
* cacheR4kDCInvalidateAll - invalidate entire R4000 data cache
*
* RETURNS: N/A
*

* void cacheR4kDCInvalidateAll (void)

*/
	.ent	cacheR4kDCInvalidateAll
FUNC_LABEL(cacheR4kDCInvalidateAll)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR4kSCacheSize
	blez	a2,1f
	lw	a3,cacheR4kSCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR4kDCacheSize
	blez	a2, 99f
	lw	a3,cacheR4kDCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheR4kDCInvalidateAll

/*******************************************************************************
*
* cacheR4kDCInvalidate - invalidate R4000 data cache locations
*
* RETURNS: N/A
*

* void cacheR4kDCInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR4kDCInvalidate
FUNC_LABEL(cacheR4kDCInvalidate)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR4kSCacheSize
	blez	a2,1f
	lw	a3,cacheR4kSCacheLineSize
	move	a1,a2
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
	b	99f

1:	lw	a2,cacheR4kDCacheSize
	blez	a2, 99f
	lw	a3,cacheR4kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
99:	j	ra
	.end	cacheR4kDCInvalidate

/*******************************************************************************
*
* cacheR4kICInvalidateAll - invalidate entire R4000 instruction cache
*
* RETURNS: N/A
*

* void cacheR4kICInvalidateAll (void)

*/
	.ent	cacheR4kICInvalidateAll
FUNC_LABEL(cacheR4kICInvalidateAll)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR4kSCacheSize
	blez	a2,1f
	lw	a3,cacheR4kSCacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
	b	98f

1:	lw	a2,cacheR4kICacheSize
	blez	a2,99f
	lw	a3,cacheR4kICacheLineSize
	li	a0,K0BASE
	move	a1,a2
	icacheop(a0,a1,a2,a3,Index_Invalidate_I)

98:	/* touch TLBHI register to clear the branch history buffer. This is */
	/* required for (at a minimum) the NEC Vr4122. */
	
	mfc0	a2, C0_TLBHI
	HAZARD_CP_READ
	mtc0	a2, C0_TLBHI
	HAZARD_TLB

99:	j	ra

	.end	cacheR4kICInvalidateAll

/*******************************************************************************
*
* cacheR4kICInvalidate - invalidate R4000 data cache locations
*
* RETURNS: N/A
*

* void cacheR4kICInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheR4kICInvalidate
FUNC_LABEL(cacheR4kICInvalidate)
	/* secondary cacheops do all the work if present */
	lw	a2,cacheR4kSCacheSize
	blez	a2,1f
	lw	a3,cacheR4kSCacheLineSize
	move	a1,a2
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
	b	98f

1:	lw	a2,cacheR4kICacheSize
	blez	a2, 99f
	lw	a3,cacheR4kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
	
98:	/* touch TLBHI register to clear the branch history buffer. This is */
	/* required for (at a minimum) the NEC Vr4122. */
	
	mfc0	a2, C0_TLBHI
	HAZARD_CP_READ
	mtc0	a2, C0_TLBHI
	HAZARD_TLB

99:	j	ra
	.end	cacheR4kICInvalidate

/******************************************************************************
*
* cacheR4kVirtPageFlush - flush one page of virtual addresses from caches
*
* Change ASID, flush the appropriate cache lines from the D- and I-cache,
* and restore the original ASID.
*
* CAVEAT: This routine and the routines it calls MAY be running to clear
* cache for an ASID which is only partially mapped by the MMU. For that
* reason, the caller may want to lock interrupts.
*
* RETURNS: N/A
*
* void cacheR4kVirtPageFlush (UINT asid, void *vAddr, UINT pageSize);
*/
	.ent	cacheR4kVirtPageFlush
FUNC_LABEL(cacheR4kVirtPageFlush)
	/* Save parameters */
	move	t4,a0			/* ASID to flush */
	move	t0,a1			/* beginning VA */
	move	t1,a2			/* length */

	/*
	 * When we change ASIDs, our stack might get unmapped,
	 * so use the stack now to free up some registers for use:
	 *	t0 - virtual base address of page to flush
	 *	t1 - page size
	 *	t2 - original SR
	 *	t3 - original ASID
	 *	t4 - ASID to flush
	 */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ	
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/* change the current ASID to context where page is mapped */

	mfc0	t3, C0_TLBHI		/* read current TLBHI */
	HAZARD_CP_READ
	and	t3, 0xff		/* extract ASID field */
	beq	t3, t4, 0f		/* branch if no need to change */
	mtc0	t4, C0_TLBHI		/* Store new EntryHi  */	
	HAZARD_TLB
0:
	/* clear the virtual addresses from D- and I-caches */
	
	lw	a2,cacheR4kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	move	a0, t0
	move	a1, t1
	lw	a3,cacheR4kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:
	lw	a2,cacheR4kICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR4kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:	
	/* restore the original ASID */

	mtc0	t3, C0_TLBHI		/* Restore old EntryHi  */	
	HAZARD_TLB

	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheR4kVirtPageFlush

/******************************************************************************
*
* cacheR4kSync - sync region of memory through all caches
*
* RETURNS: N/A
*
* void cacheR4kSync (void *vAddr, UINT pageSize);
*/
	.ent	cacheR4kSync
FUNC_LABEL(cacheR4kSync)
	/* Save parameters */
	move	t0,a0			/* beginning VA */
	move	t1,a1			/* length */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/*
	 * starting with primary caches, push the memory
	 * block out completely
	 */
	sync

	lw	a2,cacheR4kICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */
	move	a0,t0
	move	a1,t1
	lw	a3,cacheR4kICacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
1:
	lw	a2,cacheR4kDCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */
	move	a0, t0
	move	a1, t1
	lw	a3,cacheR4kDCacheLineSize
	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
1:	
	lw	a2,cacheR4kSCacheSize
	blez	a2,1f

	/* Invalidate secondary cache */
	mtc0	zero,C0_TAGLO
	mtc0	zero,C0_TAGHI
	HAZARD_CACHE_TAG

	move	a0,t0
	move	a1,t1
	lw	a3,cacheR4kSCacheLineSize
	icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
1:
	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheR4kSync