cachetx79alib.s

vxworks的源代码

	SW	ra, FRAMERA(cacheTx79RomTextUpdate)(sp)	

	/* Save the passed in parameters */
	
	sw	a0, cacheTx79ICacheSize
	sw	a1, cacheTx79ICacheLineSize
	sw	a2, cacheTx79DCacheSize
	sw	a3, cacheTx79DCacheLineSize

	/* Call PTextUpdateAll */
	
	jal	cacheTx79PTextUpdateAll

	/* restore return address */
	
	LW	ra, FRAMERA(cacheTx79RomTextUpdate)(sp)	
	addu	sp, FRAMESZ(cacheTx79RomTextUpdate)
	
	j	ra
	.end	cacheTx79RomTextUpdate
	
/******************************************************************************
*
* cacheTx79PTextUpdate - text update for entire cache.
*
* RETURNS: N/A
*

* void cacheTx79PTextUpdate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx79PTextUpdate
FUNC_LABEL(cacheTx79PTextUpdate)

	/* run from kseg1 */

	la	t0,1f
	li	t1,KSEG2_TO_KSEG0_MASK
	and	t0,t0,t1
	or	t0,K1BASE
	j	t0
1:	

	/* Save parameters */

	move	t0,a0           # virtual address
	move	t1,a1		# number of bytes to invalidate

	/* Flush-invalidate primary data cache */

	lw	a2,cacheTx79DCacheSize
	blez	a2,99f				/* Check for primary d-cache */

	lw	a3,cacheTx79DCacheLineSize
	vcacheopdw(a0,a1,a2,a3,Tx79_Hit_Writeback_Inv_D)
99:

	/* replace parameters */

	move	a0,t0		# virtual address
	move	a1,t1		# number of bytes to invalidate
	
	/* Invalidate primary instruction cache */

	lw	a2,cacheTx79ICacheSize
	blez	a2,99f				/* Check for primary i-cache */
	
	lw	a3,cacheTx79ICacheLineSize
	vcacheop(a0,a1,a2,a3,Tx79_Hit_Invalidate_I,i)
99:

	/* Invalidate primary BTAC - not required */

	j	ra
	.end	cacheTx79PTextUpdate


/*******************************************************************************
*
* cacheTx79DCFlushInvalidateAll - flush and invalidate entire Tx79 data cache
*
* RETURNS: N/A
*

* void cacheTx79DCFlushInvalidateAll (void)

*/
	.ent	cacheTx79DCFlushInvalidateAll
FUNC_LABEL(cacheTx79DCFlushInvalidateAll)

	/* Flush Invalidate the primary Data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2, 99f				/* Check for primary D-cache */
	
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	li	a0,K0BASE
	srl	a2,1		/* 2 ways are process for each address */
	move	a1,a2				/* operate on full cache */
	icacheopdw_all_ways(a0,a1,a2,a3,Tx79_Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheTx79DCFlushInvalidateAll

/*******************************************************************************
*
* cacheTx79DCFlushInvalidate - flush and invalidate Tx79 data cache locations
*
* RETURNS: N/A
*

* void cacheTx79DCFlushInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx79DCFlushInvalidate
FUNC_LABEL(cacheTx79DCFlushInvalidate)

	/* Flush Invalidate a block of primary Data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2, 99f				/* Check for primary D-cache */
	
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	vcacheopdw(a0,a1,a2,a3,Tx79_Hit_Writeback_Inv_D)
99:	j	ra
	.end	cacheTx79DCFlushInvalidate


/*******************************************************************************
*
* cacheTx79DCInvalidateAll - invalidate entire Tx79 data cache.
*
* For the _tx79xx family, this function does a flush invalidate due to the
* lack of an Indexed Invalidate operation in the CACHE instruction
*
* RETURNS: N/A
*

* void cacheTx79DCInvalidateAll (void)

*/
	.ent	cacheTx79DCInvalidateAll
FUNC_LABEL(cacheTx79DCInvalidateAll)

	/* Invalidate the primary Data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2, 99f				/* Check for primary D-cache */
	
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	li	a0,K0BASE
	srl	a2,1		/* 2 ways are process for each address */
	move	a1,a2				/* operate on full cache */
	icacheopdw_all_ways(a0,a1,a2,a3,Tx79_Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheTx79DCInvalidateAll

/*******************************************************************************
*
* cacheTx79DCInvalidate - invalidate Tx79 data cache locations
*
* RETURNS: N/A
*

* void cacheTx79DCInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx79DCInvalidate
FUNC_LABEL(cacheTx79DCInvalidate)

	/* Invalidate a block of primary Data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2, 99f				/* Check for primary D-cache */
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	vcacheop(a0,a1,a2,a3,Tx79_Hit_Invalidate_D,d)
99:	
	j	ra
	.end	cacheTx79DCInvalidate

/*******************************************************************************
*
* cacheTx79DCFlushAll - flushes entire Tx79 data cache.
*
* For the _tx79xx family, this function does a flush invalidate due to the
* lack of an Indexed Flush operation in the CACHE instruction
*
* RETURNS: N/A
*

* void cacheTx79DCFlushAll (void)

*/
	.ent	cacheTx79DCFlushAll
FUNC_LABEL(cacheTx79DCFlushAll)

	/* Flush the full primary Data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2, 99f				/* Check for primary D-cache */
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	li	a0,K0BASE
	srl	a2,1		/* 2 ways are process for each address */
	move	a1,a2				/* operate on full cache */
	icacheopdw_all_ways(a0,a1,a2,a3,Tx79_Index_Writeback_Inv_D)

99:	j	ra

	.end	cacheTx79DCFlushAll

/*******************************************************************************
*
* cacheTx79DCFlush - flush Tx79 data cache locations
*
* RETURNS: N/A
*

* void cacheTx79DCFlush
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx79DCFlush
FUNC_LABEL(cacheTx79DCFlush)

	/* Flush block from primary Data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2, 99f				/* Check for primary D-cache */
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	vcacheopdw(a0,a1,a2,a3,Tx79_Hit_Writeback_D)
99:	
	j	ra
	.end	cacheTx79DCFlush

/*******************************************************************************
*
* cacheTx79ICInvalidateAll - invalidate entire Tx79 instruction cache
*
* RETURNS: N/A
*

* void cacheTx79ICInvalidateAll (void)

*/
	.ent	cacheTx79ICInvalidateAll
FUNC_LABEL(cacheTx79ICInvalidateAll)

	/* Invalidate primary Instruction cache */

	lw	a2,cacheTx79ICacheSize		/* get I-cache size */
	blez	a2,99f				/* Check for primary I-cache */
	
	lw	a3,cacheTx79ICacheLineSize	/* get I-cache line size */
	li	a0,K0BASE
	srl	a2,1		/* 2 ways are process for each address */
	move	a1,a2
	icacheop_all_ways(a0,a1,a2,a3,Tx79_Index_Invalidate_I,i)
99:

	/* Invalidate primary BTAC */

	li	a0,K0BASE
	doopb1(Tx79_BTAC_Flush_B)

	j	ra

	.end	cacheTx79ICInvalidateAll

/*******************************************************************************
*
* cacheTx79ICInvalidate - invalidate Tx79 instruction cache locations
*
* RETURNS: N/A
*

* void cacheTx79ICInvalidate
*     (
*     baseAddr,		/@ virtual address @/
*     byteCount		/@ number of bytes to invalidate @/
*     )

*/
	.ent	cacheTx79ICInvalidate
FUNC_LABEL(cacheTx79ICInvalidate)

	/* Save parameters */

	move	t0,a0           # virtual address
	move	t1,a1		# number of bytes to invalidate

	/* Invalidate block of primary Instruction cache */

	lw	a2,cacheTx79ICacheSize		/* get I-cache size */
	blez	a2, 99f				/* Check for primary I-cache */
	
	lw	a3,cacheTx79ICacheLineSize	/* get I-cache line size */
	vcacheop(a0,a1,a2,a3,Tx79_Hit_Invalidate_I,i)
99:	

	/* Invalidate primary BTAC - not required */

	j	ra
	.end	cacheTx79ICInvalidate


#ifdef IS_KSEGM
/******************************************************************************
*
* cacheTx79VirtPageFlush - flush one page of virtual addresses from caches
*
* Change ASID, flush the appropriate cache lines from the D- and I-cache,
* and restore the original ASID.
*
* CAVEAT: This routine and the routines it calls MAY be running to clear
* cache for an ASID which is only partially mapped by the MMU. For that
* reason, the caller may want to lock interrupts.
*
* RETURNS: N/A
*
* void cacheTx79VirtPageFlush (UINT asid, void *vAddr, UINT pageSize);
*/
	.ent	cacheTx79VirtPageFlush
FUNC_LABEL(cacheTx79VirtPageFlush)
	/* Save parameters */

	move	t4,a0			/* ASID to flush */
	move	t0,a1			/* beginning VA */
	move	t1,a2			/* length */

	/*
	 * When we change ASIDs, our stack might get unmapped,
	 * so use the stack now to free up some registers for use:
	 *	t0 - virtual base address of page to flush
	 *	t1 - page size
	 *	t2 - original SR
	 *	t3 - original ASID
	 *	t4 - ASID to flush
	 */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ	
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/* change the current ASID to context where page is mapped */

	mfc0	t3, C0_TLBHI		/* read current TLBHI */
	HAZARD_CP_READ
	and	t3, 0xff		/* extract ASID field */
	beq	t3, t4, 0f		/* branch if no need to change */
	mtc0	t4, C0_TLBHI		/* Store new EntryHi  */	
	HAZARD_TLB
0:
	/* clear the virtual addresses from D- and I-caches */
	
	lw	a2,cacheTx79DCacheSize
	blez	a2,1f

	/* Flush-invalidate primary data cache */

	move	a0, t0
	move	a1, t1
	lw	a3,cacheTx79DCacheLineSize
	vcacheopdw(a0,a1,a2,a3,Tx79_Hit_Writeback_Inv_D)
1:
	lw	a2,cacheTx79ICacheSize
	blez	a2,1f	

	/* Invalidate primary instruction cache */

	move	a0,t0
	move	a1,t1
	lw	a3,cacheTx79ICacheLineSize
	vcacheop(a0,a1,a2,a3,Tx79_Hit_Invalidate_I,i)
1:	

	/* Invalidate primary BTAC - not required */

	/* restore the original ASID */

	mtc0	t3, C0_TLBHI		/* Restore old EntryHi  */	
	HAZARD_TLB

	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheTx79VirtPageFlush

/******************************************************************************
*
* cacheTx79Sync - sync region of memory through all caches
*
* RETURNS: N/A
*
* void cacheTx79Sync (void *vAddr, UINT pageSize);
*/
	.ent	cacheTx79Sync
FUNC_LABEL(cacheTx79Sync)
	
	/* Save parameters */

	move	t0,a0			/* beginning VA */
	move	t1,a1			/* length */

	/* lock interrupts */

	mfc0	t2, C0_SR
	HAZARD_CP_READ
	li	t3, ~SR_INT_ENABLE
	and	t3, t2
	mtc0	t3, C0_SR
	HAZARD_INTERRUPT

	/*
	 * starting with primary caches, push the memory
	 * block out completely
	 */

	sync

	/* Invalidate primary instruction cache */

	lw	a2,cacheTx79ICacheSize		/* get I-cache size */
	blez	a2,1f				/* Check for primary i-cache */

	move	a0,t0				/* restore virtual addr */
	move	a1,t1				/* restore length */
	lw	a3,cacheTx79ICacheLineSize	/* get I-cache line size */
	vcacheop(a0,a1,a2,a3,Tx79_Hit_Invalidate_I,i)
1:

	/* Invalidate primary BTAC - not required */

	/* Flush-invalidate primary data cache */

	lw	a2,cacheTx79DCacheSize		/* get D-cache size */
	blez	a2,1f				/* Check for primary d-cache */

	move	a0, t0				/* restore virtual addr */
	move	a1, t1				/* restore length */
	lw	a3,cacheTx79DCacheLineSize	/* get D-cache line size */
	vcacheopdw(a0,a1,a2,a3,Tx79_Hit_Writeback_Inv_D)
1:	
	mtc0	t2, C0_SR		/* restore interrupts */
	
	j	ra
	.end	cacheTx79Sync
#endif /* IS_KSEGM */