mmush7750lib.c

vxworks的源代码

/* mmuSh7750Lib.c - Hitachi SH7750 MMU support library */

/* Copyright 1996-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01s,20nov01,hk   renamed mmuTLBDump() to mmuUTLBDump(), added mmuITLBDump().
01r,23oct01,hk   allow mmucr customization by setting excMmuCrVal externally.
01q,27feb01,hk   review on-line manual pages.
01p,03aug00,hk   got rid of globalPageBlock/localMmuCr/mmuEnabled. inlined
		 MMU_UNLOCK/MMU_LOCK. disabled caching translation table on
		 virtual space. changed mmuEnable() to call mmuOn() from P1.
		 merged mmuOn()/mmuOff() and put it in mmuSh7700ALib. changed
		 mmuStateSet()/mmuPageMap() to modify PTE from P2. changed
		 mmuGlobalPageMap() to use mmuPageMap(). reduced mmuTranslate().
		 changed mmuCurrentSet() to modify TTB and flush TLB from P2.
		 moved mmuTLBFlushOp() to mmuSh7700ALib. added TLB dump tools.
01o,09oct98,hk   added cacheClear in mmuTransTblInit and mmuVirtualPageCreate.
01n,08oct98,hk   splitted again as mmuSh7750Lib. added mmuTransTblSpace.
01m,29sep98,hk   merged MMU_STATE_MASK_WRITETHROUGH to MMU_STATE_MASK_CACHEABLE.
		 deleted reference to cacheDataMode in mmuStateSet().
01l,22sep98,hms  changed mmuStateTransArrayLocal[] to support PTEL's 
                 WT(WriteThrough) bit.
                 added include file cacheShLib.h for use SH7750_PHYS_MASK,
                 SH7750_P2_BASE def.
                 modified comments. optimized.
01k,17sep98,hk   merged mmuSh7750Lib.c.
01j,14sep98,hms  (mmuSh7750Lib.c) modified comments. optimized.
01i,17aug98,hms  (mmuSh7750Lib.c) derived from mmuSh7700Lib.c-01h.
01h,25jul97,hk   doc. corrected mmu30LibInit to mmuSh7700LibInit.
01g,27apr97,hk   added CACHE_DRV_FLUSH in mmuPageAlloc().
01f,03feb97,hk   moved TTB def for manual page.
01e,18jan97,hk   added TLB init code in mmuSh7700LibInit(). added clear code
                 for PTEL table in mmuVirtualPageCreate().
01d,30dec96,hk   used intVecBaseGet() for mmuPageAlloc().
01c,28dec96,hk   code review.
01b,25dec96,hk   comment review. moved mmuEnable, mmuOn, mmuOff, mmuTLBFlush,
                 and localMmucr to mmuSh7700ALib. made mmuEnabled global.
                 gathered physical address mask code to mmuPageAlloc().
01a,08jul96,wt   derived from mmu30Lib.c.(01l?)
*/

/*
DESCRIPTION:

mmuLib.c provides the architecture dependent routines that directly control
the memory management unit.  It provides 10 routines that are called by the
higher level architecture independent routines in vmLib.c: 

mmuLibInit        - initialize module
mmuTransTblCreate - create a new translation table
mmuTransTblDelete - delete a translation table.
mmuEnable         - turn mmu on or off
mmuStateSet       - set state of virtual memory page
mmuStateGet       - get state of virtual memory page
mmuPageMap        - map physical memory page to virtual memory page
mmuGlobalPageMap  - map physical memory page to global virtual memory page
mmuTranslate      - translate a virtual address to a physical address
mmuCurrentSet     - change active translation table

Applications using the mmu will never call these routines directly; 
the visable interface is supported in vmLib.c.

mmuLib supports the creation and maintenance of multiple translation tables,
one of which is the active translation table when the mmu is enabled.
Note that VxWorks does not include a translation table as part of the task
context;  individual tasks do not reside in private virtual memory.  However,
we include the facilities to create multiple translation tables so that
the user may create "private" virtual memory contexts and switch them in an
application specific manner.  New
translation tables are created with a call to mmuTransTblCreate, and installed
as the active translation table with mmuCurrentSet.  Translation tables
are modified and potentially augmented with calls to mmuPageMap and mmuStateSet.
The state of portions of the translation table can be read with calls to
mmuStateGet and mmuTranslate.

The traditional VxWorks architecture and design philosophy requires that all
objects and operating systems resources be visable and accessable to all agents
(tasks, isrs, watchdog timers, etc) in the system.  This has traditionally been
insured by the fact that all objects and data structures reside in physical 
memory; thus, a data structure created by one agent may be accessed by any
other agent using the same pointer (object identifiers in VxWorks are often
pointers to data structures.) This creates a potential
problem if you have multiple virtual memory contexts.  For example, if a
semaphore is created in one virtual memory context, you must gurantee that
that semaphore will be visable in all virtual memory contexts if the semaphore
is to be accessed at interrupt level, when a virtual memory context other than
the one in which it was created may be active. Another example is that
code loaded using the incremental loader from the shell must be accessable
in all virtual memory contexts, since code is shared by all agents in the
system.

This problem is resolved by maintaining a global "transparent" mapping
of virtual to physical memory for all the contiguous segments of physical
memory (on board memory, i/o space, sections of vme space, etc) that is shared
by all translation tables;  all available  physical memory appears at the same 
address in virtual memory in all virtual memory contexts. This technique 
provides an environment that allows
resources that rely on a globally accessable physical address to run without
modification in a system with multiple virtual memory contexts.

An additional requirement is that modifications made to the state of global 
virtual memory in one translation table appear in all translation tables.  For
example, memory containing the text segment is made read only (to avoid
accidental corruption) by setting the appropriate writeable bits in the 
translation table entries corresponding to the virtual memory containing the 
text segment.  This state information must be shared by all virtual memory 
contexts, so that no matter what translation table is active, the text segment
is protected from corruption.  The mechanism that implements this feature is
architecture dependent, but usually entails building a section of a 
translation table that corresponds to the global memory, that is shared by
all other translation tables.  Thus, when changes to the state of the global
memory are made in one translation table, the changes are reflected in all
other translation tables.

mmuLib provides a seperate call for constructing global virtual memory -
mmuGlobalPageMap - which creates translation table entries that are shared
by all translation tables.  Initialization code in usrConfig makes calls
to vmGlobalMap (which in turn calls mmuGlobalPageMap) to set up global 
transparent virtual memory for all
available physical memory.  All calls made to mmuGlobaPageMap must occur before
any virtual memory contexts are created;  changes made to global virtual
memory after virtual memory contexts are created are not guaranteed to be
reflected in all virtual memory contexts.

Most mmu architectures will dedicate some fixed amount of virtual memory to 
a minimal section of the translation table (a "segment", or "block").  This 
creates a problem in that the user may map a small section of virtual memory
into the global translation tables, and then attempt to use the virtual memory
after this section as private virtual memory.  The problem is that the 
translation table entries for this virtual memory are contained in the global 
translation tables, and are thus shared by all translation tables.  This 
condition is detected by vmMap, and an error is returned, thus, the lower
level routines in mmuLib.c (mmuPageMap, mmuGlobalPageMap) need not perform
any error checking.

A global variable called mmuPageBlockSize should be defined which is equal to 
the minimum virtual segment size.

This module supports the SH7750 mmu with a two level translation table:

.CS
			    root
			     |
			     |
            --------------------------------
 top level  | td | td | td | td | td | td | ... 
            --------------------------------
	       |    |    |    |    |    |    
	       |    |    |    |    |    |    
      ----------    |    v    v    v    v
      |         -----   NULL NULL NULL NULL
      |         |
      v         v
     ------     ------
l   | ptel |   | ptel |
o    ------     ------
w   | ptel |   | ptel |    
e    ------     ------
r   | ptel |   | ptel |
l    ------     ------
e   | ptel |   | ptel |
v    ------     ------
e     .         .
l     .         .
      .         .
.CE

where the top level consists of an array of pointers (Table Descriptors)
held within a single
4k page.  These point to arrays of PTEL (Page Table Entry Low) arrays in
the lower level.  Each of these lower level arrays is also held within a single
4k page, and describes a virtual space of 4MB (each page
descriptor is 4 bytes, so we get 1024 of these in each array, and each page
descriptor maps a 4KB page - thus 1024 * 4096 = 4MB.)  

To implement global virtual memory, a seperate translation table called 
mmuGlobalTransTbl is created when the module is initialized.  Calls to 
mmuGlobalPageMap will augment and modify this translation table.  When new
translation tables are created, memory for the top level array of td's is
allocated and initialized by duplicating the pointers in mmuGlobalTransTbl's
top level td array.  Thus, the new translation table will use the global
translation table's state information for portions of virtual memory that are
defined as global.  Here's a picture to illustrate:

.CS
	         GLOBAL TRANS TBL		      NEW TRANS TBL

 		       root				   root
		        |				    |
		        |				    |
            -------------------------           -------------------------
 top level  | td1 | td2 | NULL| NULL|           | td1 | td2 | NULL| NULL|
            -------------------------           -------------------------
	       |     |     |     |                 |     |     |     |   
	       |     |     |     |                 |     |     |     |  
      ----------     |     v     v        ----------     |     v     v
      |         ------    NULL  NULL      |		 |    NULL  NULL
      |         |			  |		 |
      o------------------------------------		 |
      |		|					 |
      |		o-----------------------------------------
      |		|
      v         v
     ------     ------   
l   | ptel |   | ptel |
o    ------     ------
w   | ptel |   | ptel |     
e    ------     ------
r   | ptel |   | ptel |
l    ------     ------
e   | ptel |   | ptel |
v    ------     ------
e     .         .
l     .         .
      .         .
.CE

Note that with this scheme, the global memory granularity is 4MB.  Each time
you map a section of global virtual memory, you dedicate at least 4MB of 
the virtual space to global virtual memory that will be shared by all virtual
memory contexts.

The physcial memory that holds these data structures is obtained from the
system memory manager via memalign to insure that the memory is page
aligned.  We want to protect this memory from being corrupted,
so we invalidate the descriptors that we set up in the global translation
that correspond to the memory containing the translation table data structures.
This creates a "chicken and the egg" paradox, in that the only way we can
modify these data structures is through virtual memory that is now invalidated,
and we can't validate it because the page descriptors for that memory are
in invalidated memory (confused yet?)
So, you will notice that anywhere that page table descriptors (ptel's)
are modified, we do so by locking out interrupts, momentarily disabling the
mmu, accessing the memory with its physical address, enabling the mmu, and
then re-enabling interrupts (see mmuStateSet, for example.)

USER MODIFIABLE OPTIONS:

1) Memory fragmentation - mmuLib obtains memory from the system memory
   manager via memalign to contain the mmu's translation tables.  This memory
   was allocated a page at a time on page boundries.  Unfortunately, in the
   current memory management scheme, the memory manager is not able to allocate
   these pages contiguously.  Building large translation tables (ie, when
   mapping large portions of virtual memory) causes excessive fragmentation
   of the system memory pool.  An attempt to alleviate this has been installed
   by providing a local buffer of page aligned memory;  the user may control
   the buffer size by manipulating the global variable mmuNumPagesInFreeList.
   By default, mmuPagesInFreeList is set to 8.

2) Alternate memory source - A customer has special purpose hardware that
   includes seperate static RAM for the mmu's translation tables.  Thus, they
   require the ability to specify an alternate source of memory other than
   memalign.  A global variable has been created that points to the memory
   partition to be used as the source for translation table memory; by default,
   it points to the system memory partition.  The user may modify this to 
   point to another memory partition before mmuSh7750LibInit is called.
*/


#include "vxWorks.h"
#include "string.h"
#include "intLib.h"
#include "stdlib.h"
#include "memLib.h"
#include "private/memPartLibP.h"
#include "private/vmLibP.h"
#include "arch/sh/mmuSh7700Lib.h"
#include "mmuLib.h"
#include "errno.h"
#include "cacheLib.h"

/* imports */

IMPORT STATE_TRANS_TUPLE *mmuStateTransArray;		/* vmLib.c */
IMPORT int                mmuStateTransArraySize;	/* vmLib.c */
IMPORT MMU_LIB_FUNCS      mmuLibFuncs;			/* vmLib.c */
IMPORT int                mmuPageBlockSize;		/* vmLib.c */
IMPORT UINT32 excMmuCrVal;				/* excArchLib.c */

IMPORT INT32 mmuCrSetOp (INT32 val);
IMPORT INT32 mmuOnOp (BOOL enable);
IMPORT void mmuTLBFlushOp (void *v_addr);
IMPORT void mmuATTRSetOp (UINT32 *pPte, UINT32 stateMask, UINT32 state, void *v_addr);
IMPORT void mmuPPNSetOp (UINT32 *pPte, void *p_addr, void *v_addr);
IMPORT void mmuTTBSetOp (PTE *p_addr);

/* forward declarations */
 
LOCAL MMU_TRANS_TBL *mmuTransTblCreate ();
LOCAL STATUS mmuTransTblInit (MMU_TRANS_TBL *transTbl);
LOCAL STATUS mmuTransTblDelete (MMU_TRANS_TBL *transTbl);
LOCAL STATUS mmuVirtualPageCreate (MMU_TRANS_TBL *transTbl, void *v_addr);
LOCAL STATUS mmuEnable (BOOL enable);
LOCAL STATUS mmuStateGet (MMU_TRANS_TBL *transTbl, void *v_addr, UINT *state);
LOCAL STATUS mmuStateSet (MMU_TRANS_TBL *transTbl, void *v_addr, UINT stateMask, UINT state);
LOCAL STATUS mmuPageMap (MMU_TRANS_TBL *transTbl, void *v_addr, void *p_addr);
LOCAL STATUS mmuGlobalPageMap (void *v_addr, void *p_addr);
LOCAL STATUS mmuTranslate (MMU_TRANS_TBL *transTbl, void *v_addr, void **p_addr);
LOCAL STATUS mmuPteGet (MMU_TRANS_TBL *transTbl, void *v_addr, PTE **result);
LOCAL void mmuCurrentSet (MMU_TRANS_TBL *transTbl);
LOCAL void mmuTblWriteDisable (MMU_TRANS_TBL *transTbl);
LOCAL char *mmuPageAlloc (MMU_TRANS_TBL *transTbl);

/* globals */

int     mmuPageSize;
int     mmuNumPagesInFreeList = 8;
PART_ID mmuPageSource = NULL;
UINT32	mmuTransTblSpace = SH7750_P2_BASE;

/* local function pointers to relocate mmuSh7700ALib entries */

LOCAL FUNCPTR     mmuCrSet	=     (FUNCPTR)0x1234;
LOCAL FUNCPTR     mmuOn		=     (FUNCPTR)0x1234;
LOCAL VOIDFUNCPTR mmuTLBFlush	= (VOIDFUNCPTR)0x1234;
LOCAL VOIDFUNCPTR mmuATTRSet	= (VOIDFUNCPTR)0x1234;
LOCAL VOIDFUNCPTR mmuPPNSet	= (VOIDFUNCPTR)0x1234;
LOCAL VOIDFUNCPTR mmuTTBSet	= (VOIDFUNCPTR)0x1234;

/* a translation table to hold the descriptors for the global transparent
 * translation of physical to virtual memory 
 */

LOCAL MMU_TRANS_TBL mmuGlobalTransTbl;

/* initially, the current trans table is a dummy table with mmu disabled */

LOCAL MMU_TRANS_TBL *mmuCurrentTransTbl = &mmuGlobalTransTbl;


LOCAL STATE_TRANS_TUPLE mmuStateTransArrayLocal [] =		/* vmLibP.h */
    {

    {VM_STATE_MASK_VALID,             MMU_STATE_MASK_VALID,
     VM_STATE_VALID,                  MMU_STATE_VALID},

    {VM_STATE_MASK_VALID,             MMU_STATE_MASK_VALID, 
     VM_STATE_VALID_NOT,              MMU_STATE_VALID_NOT},

    {VM_STATE_MASK_WRITABLE,          MMU_STATE_MASK_WRITABLE,
     VM_STATE_WRITABLE,               MMU_STATE_WRITABLE},

    {VM_STATE_MASK_WRITABLE,          MMU_STATE_MASK_WRITABLE,
     VM_STATE_WRITABLE_NOT,           MMU_STATE_WRITABLE_NOT},

    {VM_STATE_MASK_CACHEABLE,         MMU_STATE_MASK_CACHEABLE,
     VM_STATE_CACHEABLE,              MMU_STATE_CACHEABLE},
#if (CPU==SH7750)
    {VM_STATE_MASK_CACHEABLE,         MMU_STATE_MASK_CACHEABLE,
     VM_STATE_CACHEABLE_WRITETHROUGH, MMU_STATE_CACHEABLE_WRITETHROUGH},
#endif
    {VM_STATE_MASK_CACHEABLE,         MMU_STATE_MASK_CACHEABLE,
     VM_STATE_CACHEABLE_NOT,          MMU_STATE_CACHEABLE_NOT}

    };

LOCAL MMU_LIB_FUNCS mmuLibFuncsLocal =				/* vmLibP.h */
    {
    mmuSh7750LibInit,		/* FUNCPTR mmuLibInit;        */
    mmuTransTblCreate,		/* MMU_TRANS_TBL_ID (*mmuTransTblCreate) (); */
    mmuTransTblDelete,		/* FUNCPTR mmuTransTblDelete; */
    mmuEnable,			/* FUNCPTR mmuEnable;         */
    mmuStateSet,		/* FUNCPTR mmuStateSet;       */
    mmuStateGet,		/* FUNCPTR mmuStateGet;       */
    mmuPageMap,			/* FUNCPTR mmuPageMap;        */
    mmuGlobalPageMap,		/* FUNCPTR mmuGlobalPageMap;  */
    mmuTranslate,		/* FUNCPTR mmuTranslate;      */
    mmuCurrentSet		/* VOIDFUNCPTR mmuCurrentSet; */
    };

/******************************************************************************
*
* mmuSh7750LibInit - initialize module
*
* Build a dummy translation table that will hold the page table entries for
* the global translation table.  The mmu remains disabled upon
* completion.  Note that this routine is global so that it may be referenced
* in usrConfig.c to pull in the correct mmuLib for the specific architecture.
*
* RETURNS: OK or ERROR
*/

STATUS mmuSh7750LibInit 
    (
    int pageSize
    )
    {
    PTE *v_page;
    int i;

    mmuCrSet = (FUNCPTR)(((UINT32)mmuCrSetOp
				& SH7750_PHYS_MASK) | SH7750_P1_BASE);
    mmuOn = (FUNCPTR)(((UINT32)mmuOnOp
				& SH7750_PHYS_MASK) | SH7750_P1_BASE);
    mmuTLBFlush = (VOIDFUNCPTR)(((UINT32)mmuTLBFlushOp
				& SH7750_PHYS_MASK) | SH7750_P2_BASE);
    mmuATTRSet = (VOIDFUNCPTR)(((UINT32)mmuATTRSetOp
				& SH7750_PHYS_MASK) | SH7750_P2_BASE);
    mmuPPNSet = (VOIDFUNCPTR)(((UINT32)mmuPPNSetOp
				& SH7750_PHYS_MASK) | SH7750_P2_BASE);
    mmuTTBSet = (VOIDFUNCPTR)(((UINT32)mmuTTBSetOp
				& SH7750_PHYS_MASK) | SH7750_P2_BASE);