components.vhd

来自「USBHostSlave is a USB 1.1 host and Devic」· VHDL 代码 · 共 48 行

use work.usbpkg.all;

PACKAGE usb_components IS

component hub is
         generic (
          HUBDELAY : time := 100 ns
        );

        port (
          signal downstrm_a,downstrm_b : inout pkt;
          signal upstrm : inout pkt
        );

end component;



component endpoint is
         generic (
	  MANUF: string := "FooBar Enterprises";
          ADDR : natural := 0
        );

        port (
          signal dport : inout pkt
        );

end component;



component root is
         generic (
          ADDR : natural := 0
        );

        port (
          signal dport : inout pkt
        );

end component;



END usb_components;