📄 tb_a.vhd
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library ieee;use ieee.std_logic_1164.all;library work;use work.usbpkg.all;use work.usb_components.all;entity tb_a isend tb_a;architecture a of tb_a is signal hd_1, hd_2, rc_1 : pkt;begin R0: root port map ( dport => rc_1); H0 : hub port map (downstrm_a => hd_1, downstrm_b => hd_2, upstrm => rc_1); E1: endpoint generic map (ADDR => 3, MANUF => "Cypress Mouse") port map ( dport => hd_1); E2: endpoint generic map (ADDR => 10, MANUF => "MS Natural Keyboard") port map ( dport => hd_2);end a;
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