📄 avtv32.lst
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C51 COMPILER V8.01 AVTV32 04/06/2009 11:15:27 PAGE 1
C51 COMPILER V8.01, COMPILATION OF MODULE AVTV32
OBJECT MODULE PLACED IN AVTV32.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE AVTV32.C BROWSE DEBUG OBJECTEXTEND
line level source
1 /*
2 *******************************************************************************
3 * File Name: AVTV32.C
4 * Programmed by Xiao Chunlei,2005.10.19
5 * (c) Copyright 1994-2005, Avante Electronic Technology Ltd.
6 * All Rights Reserved
7 *******************************************************************************
8 * NOTICE: If you changed this program,please write down your name
9 * and update date.
10 *******************************************************************************
11 * Update: 2006.01.22,by Xiao Chunlei (修改AVC命令与协议文档一致)
12 * Update: XXXX.XX.XX,by XXX
13 *******************************************************************************
14 */
15
16 //-----------------------------------------------------------------------------
17 // Includes
18 //-----------------------------------------------------------------------------
19
20 #include <.\Cygnal\c8051f310.h>
21 #include <string.h>
22 #include <intrins.h>
23 #include <absacc.h>
24
25 //-----------------------------------------------------------------------------
26 // 16-bit SFR Definitions for 'F31x
27 //-----------------------------------------------------------------------------
28
29 sfr16 DP = 0x82; // data pointer
30 sfr16 TMR3RL = 0x92; // Timer3 reload value
31 sfr16 TMR3 = 0x94; // Timer3 counter
32 sfr16 ADC0 = 0xBD; // ADC0 data
33 sfr16 ADC0GT = 0xC3; // ADC0 Greater-Than
34 sfr16 ADC0LT = 0xC5; // ADC0 Less-Than
35 sfr16 TMR2RL = 0xCA; // Timer2 reload value
36 sfr16 TMR2 = 0xCC; // Timer2 counter
37 sfr16 PCA0CP1 = 0xE9; // PCA0 Module 1 Capture/Compare
38 sfr16 PCA0CP2 = 0xEB; // PCA0 Module 2 Capture/Compare
39 sfr16 PCA0CP3 = 0xED; // PCA0 Module 3 Capture/Compare
40 sfr16 PCA0 = 0xF9; // PCA0 counter
41 sfr16 PCA0CP0 = 0xFB; // PCA0 Module 0 Capture/Compare
42 sfr16 PCA0CP4 = 0xFD; // PCA0 Module 4 Capture/Compare
43
44 //-----------------------------------------------------------------------------
45 // Global CONSTANTS
46 //-----------------------------------------------------------------------------
47
48 #define uchar unsigned char
49 #define uint unsigned int
50 #define ushort unsigned short
51 #define ulong unsigned long
52
53 #define FALSE 0
54 #define TRUE 1
55
C51 COMPILER V8.01 AVTV32 04/06/2009 11:15:27 PAGE 2
56 #define ON 0
57 #define OFF 1
58
59 #ifdef EXTERNAL
#define SYSCLK 32768 // SYSCLK frequency in 32768Hz
#else
62 #define SYSCLK 24500000 / 8 // SYSCLK frequency in 24.5/8 MHz
63 #endif
64
65 #define BAUDRATE 9600 // Baud rate of UART in bps
66
67 #define T0_1ms 65536L - 1 * (SYSCLK / 1000L)
68 #define T0_10ms 65536L - 10 * (SYSCLK / 1000L)
69 #define TH0S T0_10ms >> 8
70 #define TL0S T0_10ms
71
72 // Timer 2
73 #define TMR2_50us 65536L - SYSCLK / 240000L
74 #define TMR2_100us 65536L - SYSCLK / 120000L
75 #define TMR2_1ms 65536L - 1 * (SYSCLK / 12000L)
76 #define TMR2_2ms 65536L - 2 * (SYSCLK / 12000L)
77 #define TMR2_3ms 65536L - 3 * (SYSCLK / 12000L)
78 #define TMR2_4ms 65536L - 4 * (SYSCLK / 12000L)
79 #define TMR2_10ms 65536L - 10 * (SYSCLK / 12000L)
80
81 #define START_T2(X) TR2 = 0; TMR2 = X; TF2H = 0; TR2 = 1
82 #define STOP_T2() TR2 = 0
83
84 /***************************************************************************\
85 * RC531 define *
86 \***************************************************************************/
87 #define READER_INIT_RESET RSTPD = 0
88 #define READER_RESET RSTPD = 1
89 #define READER_CLEAR_RESET RSTPD = 0
90
91 #define READER_SET_NSS NSS = 0
92 #define READER_CLEAR_NSS NSS = 1
93
94 #define READER_INIT_INT IT0 = 0
95 #define READER_INT_DISABLE EX0 = 0
96 #define READER_INT_ENABLE EX0 = 1
97 /***************************************************************************\
98 * ISO14443 Command *
99 \***************************************************************************/
100 #define PICC_REQIDL 0x26 //!< request idle
101 #define PICC_REQALL 0x52 //!< request all
102 #define PICC_ANTICOLL1 0x93 //!< anticollision level 1 106 kBaud
103 #define PICC_ANTICOLL11 0x92 //!< anticollision level 1 212 kBaud
104 #define PICC_ANTICOLL12 0x94 //!< anticollision level 1 424 kBaud
105 #define PICC_ANTICOLL13 0x98 //!< anticollision level 1 848 kBaud
106 #define PICC_ANTICOLL2 0x95 //!< anticollision level 2
107 #define PICC_ANTICOLL3 0x97 //!< anticollision level 3
108 #define PICC_AUTHENT1A 0x60 //!< authentication using key A
109 #define PICC_AUTHENT1B 0x61 //!< authentication using key B
110 #define PICC_READ 0x30 //!< read block
111 #define PICC_WRITE 0xA0 //!< write block
112 #define PICC_READ16 0x30 //!< read 16 byte block
113 #define PICC_WRITE16 0xA0 //!< write 16 byte block
114 #define PICC_WRITE4 0xA2 //!< write 4 byte block
115 #define PICC_DECREMENT 0xC0 //!< decrement value
116 #define PICC_INCREMENT 0xC1 //!< increment value
117 #define PICC_RESTORE 0xC2 //!< restore command code
C51 COMPILER V8.01 AVTV32 04/06/2009 11:15:27 PAGE 3
118 #define PICC_TRANSFER 0xB0 //!< transfer command code
119 #define PICC_HALT 0x50 //!< halt
120 /***************************************************************************\
121 * RC531 register *
122 \***************************************************************************/
123 // PAGE 0 Command and Status
124 #define RegPage 0x00 //!< Page Select Register
125 #define RegCommand 0x01 //!< Command Register
126 #define RegFIFOData 0x02 //!< FiFo Register
127 #define RegPrimaryStatus 0x03 //!< Modem State/IRQ/ERR/LoHiAlert Reg
128 #define RegFIFOLength 0x04 //!< Buffer length Register
129 #define RegSecondaryStatus 0x05 //!< diverse status flags
130 #define RegInterruptEn 0x06 //!< IRQ enable Register
131 #define RegInterruptRq 0x07 //!< IRQ bits Register
132 // PAGE 1 Control and Status
133 #define RegControl 0x09 //!< processor control
134 #define RegErrorFlag 0x0A /*!< error flags showing the error
135 status of the last command executed */
136 #define RegCollPos 0x0B /*!< bit position of the first bit
137 collision detected on the
138 RF-interface */
139 #define RegTimerValue 0x0C //!< preload value of the timer
140 #define RegCRCResultLSB 0x0D //!< LSB of the CRC Coprocessor register
141 #define RegCRCResultMSB 0x0E //!< MSB of the CRC Coprocessor register
142 #define RegBitFraming 0x0F //!< Adjustments for bit oriented frames
143 // PAGE 2 Transmitter and Coder Control
144 #define RegTxControl 0x11 //!< controls the logical behaviour of
145 //!< the antenna driver pins TX1 and TX2
146 #define RegCwConductance 0x12 /*!< selects the conductance of the
147 antenna driver pins TX1 and TX2 */
148 #define RegModGsCfg 0x13 //!< RFU
149 #define RegCoderControl 0x14 //!< selects coder rate
150 #define RegModWidth 0x15 /*!< selects the width of the
151 modulation pulse */
152 #define RegModWidthSOF 0x16 //!< RFU
153 #define RegTypeBFraming 0x17 //!< RFU
154 // PAGE 3 Receiver and Decoder Control
155 #define RegRxControl1 0x19 //!< controls receiver behaviour
156 #define RegDecoderControl 0x1A //!< controls decoder behaviour
157 #define RegBitPhase 0x1B /*!< selets the bit phase between
158 transmitter and receiver clock */
159 #define RegRxThreshold 0x1C /*!< selects thresholds for the bit
160 decoder */
161 #define RegBPSKDemControl 0x1D //!< RFU
162 #define RegRxControl2 0x1E /*!< controls decoder behaviour and
163 defines the input source for the
164 receiver */
165 #define RegClockQControl 0x1F /*!< controls clock generation for the
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