avtv32.c

实现MIFARE卡操作的RC531源代码。

/*
*******************************************************************************
* File Name: AVTV32.C
* Programmed by Xiao Chunlei,2005.10.19
* (c) Copyright 1994-2005, Avante Electronic Technology Ltd.
* All Rights Reserved
*******************************************************************************
* NOTICE: If you changed this program,please write down your name
*         and update date.
*******************************************************************************
* Update: 2006.01.22,by Xiao Chunlei (修改AVC命令与协议文档一致)
* Update: XXXX.XX.XX,by XXX		
*******************************************************************************
*/

//-----------------------------------------------------------------------------
// Includes
//-----------------------------------------------------------------------------

#include <.\Cygnal\c8051f310.h>
#include <string.h>
#include <intrins.h>
#include <absacc.h>

//-----------------------------------------------------------------------------
// 16-bit SFR Definitions for 'F31x
//-----------------------------------------------------------------------------

sfr16 DP      	= 0x82;                 // data pointer
sfr16 TMR3RL   	= 0x92;                 // Timer3 reload value
sfr16 TMR3     	= 0x94;                 // Timer3 counter
sfr16 ADC0     	= 0xBD;                 // ADC0 data
sfr16 ADC0GT   	= 0xC3;                 // ADC0 Greater-Than
sfr16 ADC0LT   	= 0xC5;                 // ADC0 Less-Than
sfr16 TMR2RL   	= 0xCA;                 // Timer2 reload value
sfr16 TMR2     	= 0xCC;                 // Timer2 counter
sfr16 PCA0CP1  	= 0xE9;                 // PCA0 Module 1 Capture/Compare
sfr16 PCA0CP2  	= 0xEB;                 // PCA0 Module 2 Capture/Compare
sfr16 PCA0CP3  	= 0xED;                 // PCA0 Module 3 Capture/Compare
sfr16 PCA0     	= 0xF9;                 // PCA0 counter
sfr16 PCA0CP0  	= 0xFB;                 // PCA0 Module 0 Capture/Compare
sfr16 PCA0CP4  	= 0xFD;                 // PCA0 Module 4 Capture/Compare

//-----------------------------------------------------------------------------
// Global CONSTANTS
//-----------------------------------------------------------------------------

#define uchar		unsigned char
#define uint		unsigned int
#define ushort		unsigned short
#define ulong		unsigned long

#define FALSE		0
#define TRUE 		1

#define ON			0
#define OFF			1

#ifdef	EXTERNAL
#define SYSCLK		32768      			// SYSCLK frequency in 32768Hz
#else
#define SYSCLK		24500000 / 8   		// SYSCLK frequency in 24.5/8 MHz
#endif

#define BAUDRATE    9600           		// Baud rate of UART in bps

#define T0_1ms		65536L - 1 * (SYSCLK / 1000L)
#define T0_10ms		65536L - 10 * (SYSCLK / 1000L)
#define TH0S		T0_10ms >> 8
#define TL0S		T0_10ms

// Timer 2
#define TMR2_50us	65536L - SYSCLK / 240000L
#define TMR2_100us	65536L - SYSCLK / 120000L
#define TMR2_1ms	65536L - 1 * (SYSCLK / 12000L)
#define TMR2_2ms	65536L - 2 * (SYSCLK / 12000L)
#define TMR2_3ms	65536L - 3 * (SYSCLK / 12000L)
#define TMR2_4ms	65536L - 4 * (SYSCLK / 12000L)
#define TMR2_10ms	65536L - 10 * (SYSCLK / 12000L)

#define	START_T2(X)	TR2 = 0; TMR2 = X; TF2H = 0; TR2 = 1
#define STOP_T2()	TR2 = 0

/***************************************************************************\
*                                RC531 define                               *
\***************************************************************************/
#define READER_INIT_RESET                   RSTPD = 0
#define READER_RESET                        RSTPD = 1
#define READER_CLEAR_RESET                  RSTPD = 0

#define READER_SET_NSS						NSS = 0
#define READER_CLEAR_NSS					NSS = 1

#define READER_INIT_INT                     IT0 = 0
#define READER_INT_DISABLE                  EX0 = 0
#define READER_INT_ENABLE                   EX0 = 1
/***************************************************************************\
*                                ISO14443 Command                           *
\***************************************************************************/
#define PICC_REQIDL                         0x26         //!< request idle
#define PICC_REQALL                         0x52         //!< request all
#define PICC_ANTICOLL1                      0x93         //!< anticollision level 1 106 kBaud
#define PICC_ANTICOLL11                     0x92         //!< anticollision level 1 212 kBaud
#define PICC_ANTICOLL12                     0x94         //!< anticollision level 1 424 kBaud
#define PICC_ANTICOLL13                     0x98         //!< anticollision level 1 848 kBaud
#define PICC_ANTICOLL2                      0x95         //!< anticollision level 2
#define PICC_ANTICOLL3                      0x97         //!< anticollision level 3
#define PICC_AUTHENT1A                      0x60         //!< authentication using key A
#define PICC_AUTHENT1B                      0x61         //!< authentication using key B
#define PICC_READ                           0x30         //!< read block
#define PICC_WRITE                          0xA0         //!< write block
#define PICC_READ16                         0x30         //!< read 16 byte block
#define PICC_WRITE16                        0xA0         //!< write 16 byte block
#define PICC_WRITE4                         0xA2         //!< write 4 byte block
#define PICC_DECREMENT                      0xC0         //!< decrement value
#define PICC_INCREMENT                      0xC1         //!< increment value
#define PICC_RESTORE                        0xC2         //!< restore command code
#define PICC_TRANSFER                       0xB0         //!< transfer command code
#define PICC_HALT                           0x50         //!< halt
/***************************************************************************\
*                               RC531 register                              *
\***************************************************************************/
// PAGE 0      Command and Status
#define     RegPage               0x00   //!< Page Select Register
#define     RegCommand            0x01   //!< Command Register
#define     RegFIFOData           0x02   //!< FiFo Register
#define     RegPrimaryStatus      0x03   //!< Modem State/IRQ/ERR/LoHiAlert Reg
#define     RegFIFOLength         0x04   //!< Buffer length Register
#define     RegSecondaryStatus    0x05   //!< diverse status flags
#define     RegInterruptEn        0x06   //!< IRQ enable Register
#define     RegInterruptRq        0x07   //!< IRQ bits Register
// PAGE 1      Control and Status
#define     RegControl            0x09   //!< processor control
#define     RegErrorFlag          0x0A   /*!< error flags showing the error
                                         status of the last command executed */
#define     RegCollPos            0x0B   /*!< bit position of the first bit
                                         collision detected on the
                                         RF-interface */
#define     RegTimerValue         0x0C   //!< preload value of the timer
#define     RegCRCResultLSB       0x0D   //!< LSB of the CRC Coprocessor register
#define     RegCRCResultMSB       0x0E   //!< MSB of the CRC Coprocessor register
#define     RegBitFraming         0x0F   //!< Adjustments for bit oriented frames
// PAGE 2      Transmitter and Coder Control
#define     RegTxControl          0x11   //!< controls the logical behaviour of
                                         //!< the antenna driver pins TX1 and TX2
#define     RegCwConductance      0x12   /*!< selects the conductance of the
                                         antenna driver pins TX1 and TX2 */
#define     RegModGsCfg           0x13   //!< RFU
#define     RegCoderControl       0x14   //!< selects coder rate
#define     RegModWidth           0x15   /*!< selects the width of the
                                         modulation pulse */
#define     RegModWidthSOF        0x16   //!< RFU
#define     RegTypeBFraming       0x17   //!< RFU
// PAGE 3      Receiver and Decoder Control
#define     RegRxControl1         0x19   //!< controls receiver behaviour
#define     RegDecoderControl     0x1A   //!< controls decoder behaviour
#define     RegBitPhase           0x1B   /*!< selets the bit phase between
                                         transmitter and receiver clock */
#define     RegRxThreshold        0x1C   /*!< selects thresholds for the bit
                                         decoder */
#define     RegBPSKDemControl     0x1D   //!< RFU
#define     RegRxControl2         0x1E   /*!< controls decoder behaviour and
                                         defines the input source for the
                                         receiver */
#define     RegClockQControl      0x1F   /*!< controls clock generation for the
                                         90