cy.plg

来自「VB+proteus+keil c 文件是电压检测系统」· PLG 代码 · 共 51 行

PLG
51 行
字号 
<html>
<body>
<pre>
<h1>礦ision2 Build Log</h1>
<h2>Project:</h2>
C:\Documents and Settings\Li Junlin\桌面\电压监控\下位机程序\cy.uv2
Project File Date:  03/17/2007

<h2>Output:</h2>
Build target 'Target 1'
assembling STARTUP.A51...
assembling caiyang.asm...
caiyang.asm(184): warning A41: MISSING 'END' STATEMENT
linking...
*** WARNING L5: CODE SPACE MEMORY OVERLAP
    FROM:    0000H
    TO:      0002H
*** WARNING L1: UNRESOLVED EXTERNAL SYMBOL
    SYMBOL:  ?C_START
    MODULE:  STARTUP.obj (?C_STARTUP)
*** WARNING L2: REFERENCE MADE TO UNRESOLVED EXTERNAL
    SYMBOL:  ?C_START
    MODULE:  STARTUP.obj (?C_STARTUP)
    ADDRESS: 0124H
Program Size: data=9.0 xdata=0 code=297
creating hex file from "cy"...
"cy" - 0 Error(s), 4 Warning(s).
Build target 'Target 1'
assembling caiyang.asm...
caiyang.asm(120): warning A41: MISSING 'END' STATEMENT
linking...
*** WARNING L5: CODE SPACE MEMORY OVERLAP
    FROM:    0000H
    TO:      0002H
*** WARNING L1: UNRESOLVED EXTERNAL SYMBOL
    SYMBOL:  ?C_START
    MODULE:  STARTUP.obj (?C_STARTUP)
*** WARNING L2: REFERENCE MADE TO UNRESOLVED EXTERNAL
    SYMBOL:  ?C_START
    MODULE:  STARTUP.obj (?C_STARTUP)
    ADDRESS: 00E1H
Program Size: data=9.0 xdata=0 code=230
creating hex file from "cy"...
"cy" - 0 Error(s), 4 Warning(s).
Build target 'Target 1'
"cy" - 0 Error(s), 0 Warning(s).
Build target 'Target 1'
"cy" - 0 Error(s), 0 Warning(s).
Build target 'Target 1'
"cy" - 0 Error(s), 0 Warning(s).

cy.plg - 源码说明

本页面展示了「VB+proteus+keil c 文件是电压检测系统」中的 cy.plg 源码文件，采用 PLG 编程语言编写，共 51 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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