📄 lcd106x56.src
字号:
; lcd106x56.SRC generated from: lcd106x56.c
; COMPILER INVOKED BY:
; C:\Keil\C51\BIN\c51.exe lcd106x56.c DB OE SB ROM(COMPACT)
$NOMOD51
NAME LCD106X56
CCF2 BIT 0D8H.2
TB80 BIT 098H.3
SPI0CKR DATA 09DH
CCF3 BIT 0D8H.3
P0 DATA 080H
SPIEN BIT 0F8H.0
CCF4 BIT 0D8H.4
SM00 BIT 098H.7
P1 DATA 090H
AA BIT 0C0H.2
SM10 BIT 098H.6
WDTCN DATA 0FFH
P2 DATA 0A0H
SM20 BIT 098H.5
ADC0CF DATA 0BCH
P3 DATA 0B0H
AC BIT 0D0H.6
ADC1CF DATA 0ABH
P4 DATA 084H
EIE1 DATA 0E6H
P5 DATA 085H
EA BIT 0A8H.7
EIE2 DATA 0E7H
P6 DATA 086H
P7 DATA 096H
PSCTL DATA 08FH
MSTEN BIT 0F8H.1
CF BIT 0D8H.7
ADC0CN DATA 0E8H
DAC0CN DATA 0D4H
DAC1CN DATA 0D7H
ADC1CN DATA 0AAH
P0MDOUT DATA 0A4H
P1MDOUT DATA 0A5H
IE DATA 0A8H
P2MDOUT DATA 0A6H
P3MDOUT DATA 0A7H
TMR3RLH DATA 093H
EIP1 DATA 0F6H
EIP2 DATA 0F7H
PCA0CPH0 DATA 0FAH
PCA0CPH1 DATA 0FBH
P3IF DATA 0ADH
TMR3RLL DATA 092H
PCA0CPH2 DATA 0FCH
CR BIT 0D8H.6
PCA0CPH3 DATA 0FDH
EXF2 BIT 0C8H.6
REN0 BIT 098H.4
PCA0CPH4 DATA 0FEH
PCA0CPL0 DATA 0EAH
EMI0CF DATA 0A3H
PCA0CPL1 DATA 0EBH
PCA0CPM0 DATA 0DAH
PCA0MD DATA 0D9H
PCA0CN DATA 0D8H
PCA0CPL2 DATA 0ECH
PCA0CPM1 DATA 0DBH
PCA0CPL3 DATA 0EDH
PCA0CPM2 DATA 0DCH
IP DATA 0B8H
PCA0CPL4 DATA 0EEH
PCA0CPM3 DATA 0DDH
PCA0CPM4 DATA 0DEH
TXBSY BIT 0F8H.3
CY BIT 0D0H.7
SI BIT 0C0H.3
XBR0 DATA 0E1H
SADEN0 DATA 0B9H
XBR1 DATA 0E2H
EMI0CN DATA 0AFH
SADEN1 DATA 0AEH
XBR2 DATA 0E3H
REF0CN DATA 0D1H
SADDR0 DATA 0A9H
SADDR1 DATA 0F3H
AMX0CF DATA 0BAH
AD0INT BIT 0E8H.5
RCAP2H DATA 0CBH
PS BIT 0B8H.4
SP DATA 081H
RCAP4H DATA 0E5H
EMI0TC DATA 0A1H
OV BIT 0D0H.2
SMB0CN DATA 0C0H
RCAP2L DATA 0CAH
MODF BIT 0F8H.5
RCAP4L DATA 0E4H
SMB0CR DATA 0CFH
CPT0CN DATA 09EH
P1MDIN DATA 0BDH
CPT1CN DATA 09FH
LCD_RST BIT 0B0H.0
SPI0CN DATA 0F8H
PCON DATA 087H
SPIF BIT 0F8H.7
P74OUT DATA 0B5H
TMOD DATA 089H
TCON DATA 088H
WCOL BIT 0F8H.6
AMX0SL DATA 0BBH
AMX1SL DATA 0ACH
TMR3CN DATA 091H
LCD_CD BIT 0B0H.2
IE0 BIT 088H.1
IE1 BIT 088H.3
B DATA 0F0H
DAC0H DATA 0D3H
ADC0H DATA 0BFH
OSCICN DATA 0B2H
DAC1H DATA 0D6H
SMBFTE BIT 0C0H.1
BUSY BIT 0C0H.7
DAC0L DATA 0D2H
ADC0L DATA 0BEH
DAC1L DATA 0D5H
ACC DATA 0E0H
ES0 BIT 0A8H.4
AD0EN BIT 0E8H.7
CT2 BIT 0C8H.1
ET0 BIT 0A8H.1
LCD_CS BIT 0B0H.1
ET1 BIT 0A8H.3
TF0 BIT 088H.5
ET2 BIT 0A8H.5
RI0 BIT 098H.0
TF1 BIT 088H.7
TF2 BIT 0C8H.7
SMBTOE BIT 0C0H.0
TH0 DATA 08CH
EX0 BIT 0A8H.0
TI0 BIT 098H.1
IT0 BIT 088H.0
PCA0H DATA 0F9H
TH1 DATA 08DH
EX1 BIT 0A8H.2
IT1 BIT 088H.2
TH2 DATA 0CDH
P BIT 0D0H.0
TH4 DATA 0F5H
OSCXCN DATA 0B1H
TL0 DATA 08AH
PCA0L DATA 0E9H
TL1 DATA 08BH
TL2 DATA 0CCH
PT0 BIT 0B8H.1
TL4 DATA 0F4H
RS0 BIT 0D0H.3
PT1 BIT 0B8H.3
RS1 BIT 0D0H.4
PT2 BIT 0B8H.5
TR0 BIT 088H.4
AD0TM BIT 0E8H.6
TR1 BIT 088H.6
TR2 BIT 0C8H.2
PX0 BIT 0B8H.0
PX1 BIT 0B8H.2
SLVSEL BIT 0F8H.2
DPH DATA 083H
RCLK0 BIT 0C8H.5
ADC0GTH DATA 0C5H
TCLK0 BIT 0C8H.4
DPL DATA 082H
LCD_SDAT BIT 0B0H.6
ADC0GTL DATA 0C4H
SBUF0 DATA 099H
LCD_SCLK BIT 0B0H.4
SBUF1 DATA 0F2H
ADC0LTH DATA 0C7H
EXEN2 BIT 0C8H.3
RSTSRC DATA 0EFH
FLACL DATA 0B7H
CPRL2 BIT 0C8H.0
SCON0 DATA 098H
SCON1 DATA 0F1H
ADC0LTL DATA 0C6H
T2CON DATA 0C8H
STA BIT 0C0H.5
T4CON DATA 0C9H
SMB0ADR DATA 0C3H
SMB0DAT DATA 0C2H
SPI0CFG DATA 09AH
TMR3H DATA 095H
CKCON DATA 08EH
RXOVRN BIT 0F8H.4
TMR3L DATA 094H
AD0LJST BIT 0E8H.0
F0 BIT 0D0H.5
FLSCL DATA 0B6H
AD0CM0 BIT 0E8H.2
F1 BIT 0D0H.1
STO BIT 0C0H.4
ENSMB BIT 0C0H.6
AD0CM1 BIT 0E8H.3
SPI0DAT DATA 09BH
AD0WINT BIT 0E8H.1
ADC1 DATA 09CH
AD0BUSY BIT 0E8H.4
PSW DATA 0D0H
CCF0 BIT 0D8H.0
RB80 BIT 098H.2
SMB0STA DATA 0C1H
CCF1 BIT 0D8H.1
?PR?lcd_init?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_out_dat?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_out_ctl?LCD106X56 SEGMENT CODE INBLOCK
?PR?lcd_erase?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_test?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_clear_area?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_clear_area?LCD106X56 SEGMENT DATA OVERLAYABLE
?PR?_lcd_invert_area?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_invert_area?LCD106X56 SEGMENT DATA OVERLAYABLE
?PR?_lcd_horz_line?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_vert_line?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_clr_horz_line?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_clr_vert_line?LCD106X56 SEGMENT CODE INBLOCK
?PR?_lcd_box?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_box?LCD106X56 SEGMENT DATA OVERLAYABLE
?PR?_lcd_clr_box?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_clr_box?LCD106X56 SEGMENT DATA OVERLAYABLE
?PR?_lcd_glyph?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_glyph?LCD106X56 SEGMENT DATA OVERLAYABLE
?PR?_lcd_text?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_text?LCD106X56 SEGMENT DATA OVERLAYABLE
?PR?_lcd_update?LCD106X56 SEGMENT CODE INBLOCK
?DT?_lcd_update?LCD106X56 SEGMENT DATA OVERLAYABLE
?CO?LCD106X56 SEGMENT CODE
?XD?LCD106X56 SEGMENT XDATA
EXTRN CODE (fonts)
EXTRN CODE (?C?CLDPTR)
PUBLIC l_display_array
PUBLIC testpat
PUBLIC l_mask_array
PUBLIC _lcd_update
PUBLIC ?_lcd_text?BYTE
PUBLIC _lcd_text
PUBLIC ?_lcd_glyph?BYTE
PUBLIC _lcd_glyph
PUBLIC ?_lcd_clr_box?BYTE
PUBLIC _lcd_clr_box
PUBLIC ?_lcd_box?BYTE
PUBLIC _lcd_box
PUBLIC _lcd_clr_vert_line
PUBLIC _lcd_clr_horz_line
PUBLIC _lcd_vert_line
PUBLIC _lcd_horz_line
PUBLIC ?_lcd_invert_area?BYTE
PUBLIC _lcd_invert_area
PUBLIC ?_lcd_clear_area?BYTE
PUBLIC _lcd_clear_area
PUBLIC _lcd_test
PUBLIC lcd_erase
PUBLIC _lcd_out_ctl
PUBLIC _lcd_out_dat
PUBLIC lcd_init
RSEG ?DT?_lcd_invert_area?LCD106X56
?_lcd_invert_area?BYTE:
left?660: DS 1
top?661: DS 1
right?662: DS 1
bottom?663: DS 1
ORG 4
bit_pos?664: DS 1
RSEG ?DT?_lcd_glyph?LCD106X56
?_lcd_glyph?BYTE:
left?13108: DS 1
top?13109: DS 1
width?13110: DS 1
height?13111: DS 1
glyph?13112: DS 3
store_width?13113: DS 1
ORG 8
bit_pos?13114: DS 1
y_bits?13116: DS 1
remaining_bits?13117: DS 1
char_mask?13119: DS 1
x?13120: DS 1
glyph_offset?13122: DS 1
RSEG ?DT?_lcd_text?LCD106X56
?_lcd_text?BYTE:
left?14123: DS 1
top?14124: DS 1
font?14125: DS 1
str?14126: DS 3
ORG 6
x?14127: DS 1
glyph?14128: DS 1
width?14129: DS 1
height?14130: DS 1
store_width?14131: DS 1
glyph_ptr?14132: DS 2
RSEG ?DT?_lcd_box?LCD106X56
?_lcd_box?BYTE:
left?11100: DS 1
top?11101: DS 1
right?11102: DS 1
bottom?11103: DS 1
RSEG ?DT?_lcd_clr_box?LCD106X56
?_lcd_clr_box?BYTE:
left?12104: DS 1
top?12105: DS 1
right?12106: DS 1
bottom?12107: DS 1
RSEG ?DT?_lcd_clear_area?LCD106X56
?_lcd_clear_area?BYTE:
left?550: DS 1
top?551: DS 1
right?552: DS 1
bottom?553: DS 1
ORG 4
bit_pos?554: DS 1
RSEG ?DT?_lcd_update?LCD106X56
?_lcd_update?BYTE:
y?15136: DS 1
yb?15138: DS 1
colptr?15139: DS 3
RSEG ?XD?LCD106X56
l_display_array: DS 848
RSEG ?CO?LCD106X56
l_mask_array:
DB 001H
DB 002H
DB 004H
DB 008H
DB 010H
DB 020H
DB 040H
DB 080H
testpat:
DB 00FH
DB 00FH
DB 00FH
DB 00FH
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 0F0H
DB 00FH
DB 00FH
DB 00FH
DB 00FH
DB 0FFH
DB 081H
DB 0BDH
DB 0BDH
DB 0BDH
DB 0BDH
DB 081H
DB 0FFH
DB 000H
DB 07EH
DB 042H
DB 042H
DB 042H
DB 042H
DB 07EH
DB 000H
; #pragma SRC
; /***************************************************************************
; * *
; * FILE: LCD106x56.C *
; * LCD Display Controller Interface Routines for use with Tian-ma *
; * 106x56 Graphics module with onboard S6B0724X01-B0CY controller *
; * *
; * Copyright (C) 2003 by Carousel Design Solutions *
; * *
; * Written by: *
; * Michael J. Karas *
; * Carousel Design Solutions *
; * 4217 Grimes Ave South *
; * Edina MN 55416 *
; * (952) 929-7537 *
; * *
; ***************************************************************************/
;
; #pragma CODE
;
; #include <c8051f020.h> // SFR declarations
; #include "lcd106x56.h"
; #include "fonts.h"
;
; /* pixel level bit masks for display */
; /* this array is setup to map the order */
; /* of bits in a byte to the vertical order */
; /* of bits at the LCD controller */
; const unsigned char code l_mask_array[8] =
; {0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80};
;
; /* the LCD display image memory */
; /* buffer arranged so page memory is sequential in RAM */
; unsigned char xdata l_display_array[Y_BYTES][X_BYTES];
;
; /*
; **
; ** Low level LCD Controller Interface Support Routines
; ** The LCD Controller interfaces to the microcontroller
; ** using the connections as shown below.
; **
; ** P3^0 LCD Controller Reset (RST/) signal
; ** P3^1 LCD Controller Chip Select (CS/) signal
; ** P3^2 LCD Controller Ctl/Data Select (C/D) signal
; ** P3^2 LCD Controller Serial Clcok (SCLK) signal
; ** P3^3 LCD Controller Serial Data (SDAT) signal
; **
; **
; */
;
; /*
; **
; ** routine to initialize the operation of the LCD display subsystem
; **
; */
;
; void lcd_init(void)
RSEG ?PR?lcd_init?LCD106X56
lcd_init:
USING 0
; SOURCE LINE # 57
; {
; SOURCE LINE # 58
; int i;
;
; /* initialize the port control lines to the LCD module */
; LCD_RST = 1; /* set RST signal high off output */
; SOURCE LINE # 62
SETB LCD_RST
;
; LCD_CS = 1; /* set chip select high off output */
; SOURCE LINE # 64
SETB LCD_CS
;
; LCD_CD = 0; /* set the CD line low as output */
; SOURCE LINE # 66
CLR LCD_CD
;
; LCD_SCLK = 1; /* set SCLK line high */
; SOURCE LINE # 68
SETB LCD_SCLK
;
; LCD_SDAT = 0; /* set SDAT line low */
; SOURCE LINE # 70
CLR LCD_SDAT
;
; /* reset the LCD controller chip */
; LCD_RST = 0; /* set the reset line low */
; SOURCE LINE # 73
CLR LCD_RST
; for(i=0; i<1000; i++) /* delay for the reset time */
; SOURCE LINE # 74
;---- Variable 'i?040' assigned to Register 'R6/R7' ----
CLR A
MOV R7,A
MOV R6,A
?C0001:
; {
; SOURCE LINE # 75
; }
; SOURCE LINE # 76
INC R7
CJNE R7,#00H,?C0119
INC R6
?C0119:
CJNE R6,#03H,?C0001
CJNE R7,#0E8H,?C0001
?C0002:
; LCD_RST = 1; /* release reset to back high */
; SOURCE LINE # 77
SETB LCD_RST
;
; /* program the controller operational state */
; lcd_out_ctl(LCD_SET_ADC_REV); /* set ADC reverse */
; SOURCE LINE # 80
MOV R7,#0A1H
LCALL _lcd_out_ctl
; lcd_out_ctl(LCD_SET_SHL_NOR); /* set SHL normal */
; SOURCE LINE # 81
MOV R7,#0C0H
LCALL _lcd_out_ctl
; lcd_out_ctl(LCD_SET_BIAS_0); /* set for the low bias mode */
; SOURCE LINE # 82
MOV R7,#0A2H
LCALL _lcd_out_ctl
; lcd_out_ctl(LCD_PWR_CTL+5); /* turn on the VC bit */
; SOURCE LINE # 83
MOV R7,#02DH
LCALL _lcd_out_ctl
; for(i=0; i<1000; i++) /* delay for the converter on */
; SOURCE LINE # 84
CLR A
MOV R6,A
MOV R7,A
?C0004:
; {
; SOURCE LINE # 85
; }
; SOURCE LINE # 86
INC R7
CJNE R7,#00H,?C0120
INC R6
?C0120:
CJNE R6,#03H,?C0004
CJNE R7,#0E8H,?C0004
?C0005:
; lcd_out_ctl(LCD_PWR_CTL+6); /* now turn on VC+VR bits */
; SOURCE LINE # 87
MOV R7,#02EH
LCALL _lcd_out_ctl
; for(i=0; i<1000; i++) /* delay for the regulator on */
; SOURCE LINE # 88
CLR A
MOV R6,A
MOV R7,A
?C0007:
; {
; SOURCE LINE # 89
; }
; SOURCE LINE # 90
INC R7
CJNE R7,#00H,?C0121
INC R6
?C0121:
CJNE R6,#03H,?C0007
CJNE R7,#0E8H,?C0007
?C0008:
; lcd_out_ctl(LCD_PWR_CTL+7); /* now turn on the VC+VR+VF */
; SOURCE LINE # 91
MOV R7,#02FH
LCALL _lcd_out_ctl
; lcd_out_ctl(LCD_REG_RESISTOR+4); /* set default resistor ratio */
; SOURCE LINE # 92
MOV R7,#024H
LCALL _lcd_out_ctl
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -