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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file g:/girija/fpga/bcd_7seg/bcd_7seg.vhd in Library work.Entity <bcd_7seg> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <bcd_7seg> (Architecture <Behavioral>).Entity <bcd_7seg> analyzed. Unit <bcd_7seg> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <bcd_7seg>. Related source file is g:/girija/fpga/bcd_7seg/bcd_7seg.vhd.WARNING:Xst:1306 - Output <en3> is never assigned.WARNING:Xst:1306 - Output <en4> is never assigned. Found 16x8-bit ROM for signal <dis_out>. Summary: inferred 1 ROM(s).Unit <bcd_7seg> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <bcd_7seg> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bcd_7seg, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 4 out of 768 0% Number of 4 input LUTs: 8 out of 1536 0% Number of bonded IOBs: 15 out of 124 12% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.355ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file g:/girija/fpga/bcd_7seg/bcd_7seg.vhd in Library work.Entity <bcd_7seg> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <bcd_7seg> (Architecture <behavioral>).INFO:Xst:1304 - Contents of register <en3> in unit <bcd_7seg> never changes during circuit operation. The register is replaced by logic.INFO:Xst:1304 - Contents of register <en4> in unit <bcd_7seg> never changes during circuit operation. The register is replaced by logic.Entity <bcd_7seg> analyzed. Unit <bcd_7seg> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <bcd_7seg>. Related source file is g:/girija/fpga/bcd_7seg/bcd_7seg.vhd. Found 16x8-bit ROM for signal <dis_out>. Summary: inferred 1 ROM(s).Unit <bcd_7seg> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <bcd_7seg> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bcd_7seg, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 4 out of 768 0% Number of 4 input LUTs: 8 out of 1536 0% Number of bonded IOBs: 17 out of 124 13% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.355ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_7seg/_ngo -i -pxc3s50-pq208-5 bcd_7seg.ngc bcd_7seg.ngd Reading NGO file "g:/girija/fpga/bcd_7seg/bcd_7seg.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 36040 kilobytesWriting NGD file "bcd_7seg.ngd" ...Writing NGDBUILD log file "bcd_7seg.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_7seg/_ngo -ucbcd_7seg.ucf -p xc3s50-pq208-5 bcd_7seg.ngc bcd_7seg.ngd Reading NGO file "g:/girija/fpga/bcd_7seg/bcd_7seg.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "bcd_7seg.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 38088 kilobytesWriting NGD file "bcd_7seg.ngd" ...Writing NGDBUILD log file "bcd_7seg.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "3s50pq208-5".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 7 out of 1,536 1%Logic Distribution: Number of occupied Slices: 4 out of 768 1% Number of Slices containing only related logic: 4 out of 4 100% Number of Slices containing unrelated logic: 0 out of 4 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 7 out of 1,536 1% Number of bonded IOBs: 17 out of 124 13%Total equivalent gate count for design: 42Additional JTAG gate count for IOBs: 816Peak Memory Usage: 62 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "bcd_7seg_map.mrp" for details.Completed process "Map".Mapping Module bcd_7seg . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o bcd_7seg_map.ncd bcd_7seg.ngd bcd_7seg.pcf
Mapping Module bcd_7seg: DONE
Started process "Place & Route".Constraints file: bcd_7seg.pcfLoading device database for application Par from file "bcd_7seg_map.ncd". "bcd_7seg" is an NCD, version 2.38, device xc3s50, package pq208, speed -5Loading device for application Par from file '3s50.nph' in environmentE:/Xilinx.Device speed data version: ADVANCED 1.32 2004-06-25.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External IOBs 17 out of 124 13% Number of LOCed External IOBs 17 out of 17 100% Number of Slices 4 out of 768 1%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9896a9) REAL time: 2 secs Phase 3.8.Phase 3.8 (Checksum:98a813) REAL time: 2 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.18Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs Writing design to file bcd_7seg.ncd.Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Phase 1: 40 unrouted; REAL time: 2 secs Phase 2: 40 unrouted; REAL time: 2 secs Phase 3: 0 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "par" statistics.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 49 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file bcd_7seg.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Mon Apr 25 14:04:05 2005--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module bcd_7seg . . .
PAR command line: par -w -intstyle ise -ol std -t 1 bcd_7seg_map.ncd bcd_7seg.ncd bcd_7seg.pcf
PAR completed successfully
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_7seg/_ngo -ucbcd_7seg.ucf -p xc3s50-pq208-5 bcd_7seg.ngc bcd_7seg.ngd Reading NGO file "G:/GIRIJA/FPGA/bcd_7seg/bcd_7seg.ngc" ...Reading component libraries for design expansion...⌨️ 快捷键说明
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