bcd_7seg.par

this program will give the functionality of bcd to seven segment display

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

P4::  Thu Feb 16 11:03:04 2006


E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 bcd_7seg_map.ncd
bcd_7seg.ncd bcd_7seg.pcf 


Constraints file: bcd_7seg.pcf

Loading device database for application Par from file "bcd_7seg_map.ncd".
   "bcd_7seg" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolved that IOB <count<0>> must be placed at site P35.
Resolved that IOB <count<1>> must be placed at site P29.
Resolved that IOB <count<2>> must be placed at site P27.
Resolved that IOB <count<3>> must be placed at site P21.
Resolved that IOB <en1> must be placed at site P2.
Resolved that IOB <en2> must be placed at site P3.
Resolved that IOB <en3> must be placed at site P7.
Resolved that IOB <en4> must be placed at site P9.
Resolved that IOB <dis_out<0>> must be placed at site P10.
Resolved that IOB <dis_out<1>> must be placed at site P11.
Resolved that IOB <dis_out<2>> must be placed at site P12.
Resolved that IOB <dis_out<3>> must be placed at site P13.
Resolved that IOB <dis_out<4>> must be placed at site P15.
Resolved that IOB <dis_out<5>> must be placed at site P16.
Resolved that IOB <dis_out<6>> must be placed at site P18.
Resolved that IOB <dis_out<7>> must be placed at site P19.


Device utilization summary:

   Number of External IOBs            16 out of 124    12%
      Number of LOCed External IOBs   16 out of 16    100%

   Number of Slices                    4 out of 768     1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896a7) REAL time: 2 secs 

Phase 3.8
.
Phase 3.8 (Checksum:98a4e9) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file bcd_7seg.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 40 unrouted;       REAL time: 2 secs 

Phase 2: 35 unrouted;       REAL time: 2 secs 

Phase 3: 14 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 85


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.700
   The MAXIMUM PIN DELAY IS:                               1.210
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.747

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          35           5           0           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file bcd_7seg.ncd.


PAR done.