bcd_7seg_sch.vhf

this program will give the functionality of bcd to seven segment display

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : bcd_7seg_sch.vhf
-- /___/   /\     Timestamp : 03/09/2006 14:52:27
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: D3_8E_MXILINX_bcd_7seg_sch
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity D3_8E_MXILINX_bcd_7seg_sch is
   port ( A0 : in    std_logic; 
          A1 : in    std_logic; 
          A2 : in    std_logic; 
          E  : in    std_logic; 
          D0 : out   std_logic; 
          D1 : out   std_logic; 
          D2 : out   std_logic; 
          D3 : out   std_logic; 
          D4 : out   std_logic; 
          D5 : out   std_logic; 
          D6 : out   std_logic; 
          D7 : out   std_logic);
end D3_8E_MXILINX_bcd_7seg_sch;

architecture BEHAVIORAL of D3_8E_MXILINX_bcd_7seg_sch is
   attribute BOX_TYPE   : string ;
   component AND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
   
   component AND4B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX";
   
   component AND4B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX";
   
   component AND4B3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX";
   
begin
   I_36_30 : AND4
      port map (I0=>A2,      
                I1=>A1,      
                I2=>A0,      
                I3=>E,      
                O=>D7);
   
   I_36_31 : AND4B1
      port map (I0=>A0,      
                I1=>A2,      
                I2=>A1,      
                I3=>E,      
                O=>D6);
   
   I_36_32 : AND4B1
      port map (I0=>A1,      
                I1=>A2,      
                I2=>A0,      
                I3=>E,      
                O=>D5);
   
   I_36_33 : AND4B2
      port map (I0=>A1,      
                I1=>A0,      
                I2=>A2,      
                I3=>E,      
                O=>D4);
   
   I_36_34 : AND4B1
      port map (I0=>A2,      
                I1=>A0,      
                I2=>A1,      
                I3=>E,      
                O=>D3);
   
   I_36_35 : AND4B2
      port map (I0=>A2,      
                I1=>A0,      
                I2=>A1,      
                I3=>E,      
                O=>D2);
   
   I_36_36 : AND4B2
      port map (I0=>A2,      
                I1=>A1,      
                I2=>A0,      
                I3=>E,      
                O=>D1);
   
   I_36_37 : AND4B3
      port map (I0=>A2,      
                I1=>A1,      
                I2=>A0,      
                I3=>E,      
                O=>D0);
   
end BEHAVIORAL;


--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : bcd_7seg_sch.vhf
-- /___/   /\     Timestamp : 03/09/2006 14:52:27
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: bcd_7seg_sch
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity bcd_7seg_sch is
   port ( count   : in    std_logic_vector (3 downto 0); 
          sel     : in    std_logic; 
          display : out   std_logic_vector (7 downto 0); 
          en1     : out   std_logic; 
          en2     : out   std_logic; 
          en3     : out   std_logic; 
          en4     : out   std_logic);
end bcd_7seg_sch;

architecture BEHAVIORAL of bcd_7seg_sch is
   attribute HU_SET     : string ;
   component bcd_7seg
      port ( sel     : in    std_logic; 
             count   : in    std_logic_vector (3 downto 0); 
             en1     : out   std_logic; 
             en2     : out   std_logic; 
             en3     : out   std_logic; 
             en4     : out   std_logic; 
             dis_out : out   std_logic_vector (7 downto 0));
   end component;
   
   component D3_8E_MXILINX_bcd_7seg_sch
      port ( A0 : in    std_logic; 
             A1 : in    std_logic; 
             A2 : in    std_logic; 
             E  : in    std_logic; 
             D0 : out   std_logic; 
             D1 : out   std_logic; 
             D2 : out   std_logic; 
             D3 : out   std_logic; 
             D4 : out   std_logic; 
             D5 : out   std_logic; 
             D6 : out   std_logic; 
             D7 : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_2 : label is "XLXI_2_0";
begin
   XLXI_1 : bcd_7seg
      port map (count(3 downto 0)=>count(3 downto 0),      
                sel=>sel,      
                dis_out(7 downto 0)=>display(7 downto 0),      
                en1=>en1,      
                en2=>en2,      
                en3=>en3,      
                en4=>en4);
   
   XLXI_2 : D3_8E_MXILINX_bcd_7seg_sch
      port map (A0=>open,      
                A1=>open,      
                A2=>open,      
                E=>open,      
                D0=>open,      
                D1=>open,      
                D2=>open,      
                D3=>open,      
                D4=>open,      
                D5=>open,      
                D6=>open,      
                D7=>open);
   
end BEHAVIORAL;