bcd_7seg.npl

来自「this program will give the functionality」· NPL 代码 · 共 32 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT bcd_7seg
DESIGN bcd_7seg
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s50
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE bcd_7seg.vhd
SOURCE bcd_7seg_sch.sch
DEPASSOC bcd_7seg bcd_7seg.ucf
[Normal]
xilxBitgCfg_GenOpt_MaskFile=xstvhd, spartan3, Implementation.t_bitFile, 1114418056, True
xilxBitgCfg_GenOpt_ReadBack_Spartan3=xstvhd, spartan3, Implementation.t_bitFile, 1114418056, True
xilxBitgStart_Clk=xstvhd, spartan3, Implementation.t_bitFile, 1115181488, JTAG Clock
[STATUS-ALL]
bcd_7seg_sch.ngcFileGroup=NOT_RUN,0
[STRATEGY-LIST]
Normal=True