bcd_7seg_sch.syr

来自「this program will give the functionality」· SYR 代码 · 共 107 行

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.78 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: bcd_7seg_sch.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : bcd_7seg_sch.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : bcd_7seg_sch
Output Format                      : NGC
Target Device                      : xc3s50-5-pq208

---- Source Options
Top Module Name                    : bcd_7seg_sch
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : ONLY
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : bcd_7seg_sch.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd in Library work.
Entity <bcd_7seg> (Architecture <behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf in Library work.
Entity <D3_8E_MXILINX_bcd_7seg_sch> (Architecture <BEHAVIORAL>) compiled.
ERROR:HDLParsers:856 - G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf Line 215. No default value for unconnected port <A0>.
ERROR:HDLParsers:856 - G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf Line 216. No default value for unconnected port <A1>.
ERROR:HDLParsers:856 - G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf Line 217. No default value for unconnected port <A2>.
ERROR:HDLParsers:856 - G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf Line 218. No default value for unconnected port <E>.
ERROR:HDLParsers:900 - G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg_sch.vhf Line 228. The label XLXI_2 is not declared.
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Total memory usage is 45304 kilobytes