bcd_7seg.syr

this program will give the functionality of bcd to seven segment display

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: bcd_7seg.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : bcd_7seg.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : bcd_7seg
Output Format                      : NGC
Target Device                      : xc3s50-5-pq208

---- Source Options
Top Module Name                    : bcd_7seg
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : ONLY
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : bcd_7seg.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd in Library work.
Architecture behavioral of Entity bcd_7seg is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <bcd_7seg> (Architecture <behavioral>).
Entity <bcd_7seg> analyzed. Unit <bcd_7seg> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <bcd_7seg>.
    Related source file is G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd.
    Found 16x8-bit ROM for signal <dis_out>.
    Summary:
	inferred   1 ROM(s).
Unit <bcd_7seg> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : bcd_7seg.ngr
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Cell Usage :
# BELS                             : 2
#      GND                         : 1
#      VCC                         : 1
=========================================================================
CPU : 8.81 / 10.38 s | Elapsed : 9.00 / 10.00 s
 
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Total memory usage is 51448 kilobytes