__projnav.log

this program give the functionality bcd count

Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_cntr/_ngo -uc
bcd_cntr.ucf -p xc3s50-pq208-5 bcd_cntr.ngc bcd_cntr.ngd 

Reading NGO file "G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "bcd_cntr.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38088 kilobytes

Writing NGD file "bcd_cntr.ngd" ...

Writing NGDBUILD log file "bcd_cntr.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s50pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:           8 out of   1,536    1%
  Number of 4 input LUTs:              15 out of   1,536    1%
Logic Distribution:
  Number of occupied Slices:                           11 out of     768    1%
    Number of Slices containing only related logic:      11 out of      11  100%
    Number of Slices containing unrelated logic:          0 out of      11    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             22 out of   1,536    1%
  Number used as logic:                 15
  Number used as a route-thru:           7
  Number of bonded IOBs:               11 out of     124    8%
    IOB Flip Flops:                     8

Total equivalent gate count for design:  260
Additional JTAG gate count for IOBs:  528
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "bcd_cntr_map.mrp" for details.
Completed process "Map".

Mapping Module bcd_cntr . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o bcd_cntr_map.ncd bcd_cntr.ngd bcd_cntr.pcf
Mapping Module bcd_cntr: DONE



Started process "Place & Route".





Constraints file: bcd_cntr.pcf

Loading device database for application Par from file "bcd_cntr_map.ncd".
   "bcd_cntr" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            11 out of 124     8%
      Number of LOCed External IOBs   11 out of 11    100%

   Number of Slices                   11 out of 768     1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896b8) REAL time: 2 secs 

WARNING:Place:410 - The input design contains local clock signal(s). To get the
   better result, we recommend users run map with the "-timing" option set
   before starting the placement.
Phase 3.8
.
Phase 3.8 (Checksum:98b1eb) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file bcd_cntr.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 106 unrouted;       REAL time: 3 secs 

Phase 2: 92 unrouted;       REAL time: 3 secs 

Phase 3: 23 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|            bpulse       |   Local  |      |   14 |  0.072     |  2.131      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file bcd_cntr.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Tue Jun 07 12:06:25 2005
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module bcd_cntr . . .
PAR command line: par -w -intstyle ise -ol std -t 1 bcd_cntr_map.ncd bcd_cntr.ncd bcd_cntr.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd in Library work.
Architecture behavioral of Entity divd10 is up to date.
Compiling vhdl file G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd in Library work.
ERROR:HDLParsers:3312 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd Line 53. Undefined symbol 'clk'.
ERROR:HDLParsers:1209 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd Line 53. clk: Undefined symbol (last report in this block)
ERROR:HDLParsers:851 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd Line 52. Formal clk of testcnt with no default value must be associated with an actual value.
--> 

Total memory usage is 48316 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd in Library work.
Architecture behavioral of Entity divd10 is up to date.
Compiling vhdl file G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd in Library work.
ERROR:HDLParsers:1202 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd Line 53. Redeclaration of symbol u1.
--> 

Total memory usage is 48316 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd in Library work.
Architecture behavioral of Entity divd10 is up to date.
Compiling vhdl file G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd in Library work.
Entity <bcd_cntr> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <bcd_cntr> (Architecture <behavioral>).
WARNING:Xst:766 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd line 52: Generating a Black Box for component <ibuf>.
Entity <bcd_cntr> analyzed. Unit <bcd_cntr> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <divd10> (Architecture <behavioral>).
Entity <divd10> analyzed. Unit <divd10> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <divd10>.
    Related source file is F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd.
    Found 3-bit comparator less for signal <$n0003> created at line 22.
    Found 3-bit up counter for signal <dvd10>.
    Found 1-bit register for signal <t>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <divd10> synthesized.


Synthesizing Unit <testcnt>.
    Related source file is F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd.
    Found 1-bit register for signal <one>.
    Found 1-bit register for signal <check>.
    Found 8-bit up counter for signal <cnt>.
    Found 1-bit register for signal <t>.
    Summary:
	inferred   1 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <testcnt> synthesized.


Synthesizing Unit <bcd_cntr>.
    Related source file is G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd.
WARNING:Xst:653 - Signal <rowtemp> is used but never assigned. Tied to value 0.
ERROR:Xst:1534 - Sequential logic for node <count1> appears to be controlled by multiple clocks.
ERROR:Xst:739 - Failed to synthesize logic for signal <count1>.
ERROR:Xst:1431 - Failed to synthesize unit <bcd_cntr>.
--> 

Total memory usage is 54460 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd in Library work.
Architecture behavioral of Entity divd10 is up to date.
Compiling vhdl file G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd in Library work.
Entity <bcd_cntr> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <bcd_cntr> (Architecture <behavioral>).
WARNING:Xst:766 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd line 52: Generating a Black Box for component <ibuf>.
Entity <bcd_cntr> analyzed. Unit <bcd_cntr> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <divd10> (Architecture <behavioral>).
Entity <divd10> analyzed. Unit <divd10> generated.