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Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage: 51 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file bcd_cntr.ncd.PAR done.Completed process "Place & Route".Started process "Generate Post-Place & Route Static Timing".Analysis completed Tue Jun 07 10:52:03 2005--------------------------------------------------------------------------------Generating Report ...Completed process "Generate Post-Place & Route Static Timing".Place & Route Module bcd_cntr . . .
PAR command line: par -w -intstyle ise -ol std -t 1 bcd_cntr_map.ncd bcd_cntr.ncd bcd_cntr.pcf
PAR completed successfully
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd in Library work.Architecture behavioral of Entity divd10 is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <divd10> (Architecture <behavioral>).Entity <divd10> analyzed. Unit <divd10> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <divd10>. Related source file is F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd. Found 3-bit comparator less for signal <$n0003> created at line 22. Found 3-bit up counter for signal <dvd10>. Found 1-bit register for signal <t>. Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). inferred 1 Comparator(s).Unit <divd10> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 1 3-bit up counter : 1# Registers : 1 1-bit register : 1# Comparators : 1 3-bit comparator less : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <divd10> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block divd10, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 2 out of 768 0% Number of Slice Flip Flops: 4 out of 1536 0% Number of 4 input LUTs: 4 out of 1536 0% Number of bonded IOBs: 1 out of 124 0% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clkin | BUFGP | 4 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 2.176ns (Maximum Frequency: 459.559MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 5.331ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_cntr/_ngo -i -pxc3s50-pq208-5 divd10.ngc divd10.ngd Reading NGO file "G:/GIRIJA/FPGA/bcd_cntr/divd10.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 36040 kilobytesWriting NGD file "divd10.ngd" ...Writing NGDBUILD log file "divd10.bld"...NGDBUILD done.Completed process "Translate".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd in Library work.Entity <bcd_cntr> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <bcd_cntr> (Architecture <behavioral>).WARNING:Xst:766 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd line 39: Generating a Black Box for component <ibuf>.ERROR:Xst:797 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd line 45: unsupported Clock statement.--> Total memory usage is 54460 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd in Library work.Entity <bcd_cntr> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <bcd_cntr> (Architecture <behavioral>).WARNING:Xst:766 - G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd line 39: Generating a Black Box for component <ibuf>.Entity <bcd_cntr> analyzed. Unit <bcd_cntr> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <bcd_cntr>. Related source file is G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.vhd.WARNING:Xst:653 - Signal <rowtemp> is used but never assigned. Tied to value 0. Found 1-bit register for signal <row>. Found 4-bit register for signal <count>. Found 4-bit register for signal <count1>. Found 8-bit adder for signal <$n0000> created at line 49. Found 4-bit adder for signal <$n0001> created at line 52. Found 8-bit comparator lessequal for signal <$n0027> created at line 54. Found 8-bit comparator greatequal for signal <$n0028> created at line 50. Found 8-bit comparator greater for signal <$n0030> created at line 54. Found 8-bit register for signal <cnt1>. Summary: inferred 17 D-type flip-flop(s). inferred 2 Adder/Subtracter(s). inferred 3 Comparator(s).Unit <bcd_cntr> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 2 8-bit adder : 1 4-bit adder : 1# Registers : 11 1-bit register : 9 4-bit register : 2# Comparators : 3 8-bit comparator greater : 1 8-bit comparator greatequal : 1 8-bit comparator lessequal : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <row> (without init value) is constant in block <bcd_cntr>.WARNING:Xst:1988 - Unit <bcd_cntr>: instances <Mcompar__n0027>, <Mcompar__n0030> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_3> are dual, second instance is removedOptimizing unit <bcd_cntr> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block bcd_cntr, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 16 out of 768 2% Number of Slice Flip Flops: 16 out of 1536 1% Number of 4 input LUTs: 22 out of 1536 1% Number of bonded IOBs: 11 out of 124 8% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+pulse | IBUF | 16 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 4.183ns (Maximum Frequency: 239.063MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 5.106ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_cntr/_ngo -i -pxc3s50-pq208-5 bcd_cntr.ngc bcd_cntr.ngd Reading NGO file "G:/GIRIJA/FPGA/bcd_cntr/bcd_cntr.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 36040 kilobytesWriting NGD file "bcd_cntr.ngd" ...Writing NGDBUILD log file "bcd_cntr.bld"...NGDBUILD done.Completed process "Translate".⌨️ 快捷键说明
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