__projnav.log

this program give the functionality bcd count

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd in Library work.
Entity <testcnt> (Architecture <Behavioral>) compiled.
Compiling vhdl file F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd in Library work.
Entity <divd10> (Architecture <Behavioral>) compiled.
Compiling vhdl file g:/girija/fpga/bcd_cntr/bcd_cntr.vhd in Library work.
Entity <bcd_cntr> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <bcd_cntr> (Architecture <Behavioral>).
Entity <bcd_cntr> analyzed. Unit <bcd_cntr> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <divd10> (Architecture <behavioral>).
Entity <divd10> analyzed. Unit <divd10> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <divd10>.
    Related source file is F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/divd10.vhd.
    Found 3-bit comparator less for signal <$n0003> created at line 22.
    Found 3-bit up counter for signal <dvd10>.
    Found 1-bit register for signal <t>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <divd10> synthesized.


Synthesizing Unit <testcnt>.
    Related source file is F:/PUSHPA/cpld_trainer/softwares/UPDOWNCNT_C/testcnt.vhd.
    Found 1-bit register for signal <one>.
    Found 1-bit register for signal <check>.
    Found 8-bit up counter for signal <cnt>.
    Found 1-bit register for signal <t>.
    Summary:
	inferred   1 Counter(s).
	inferred   3 D-type flip-flop(s).
Unit <testcnt> synthesized.


Synthesizing Unit <bcd_cntr>.
    Related source file is g:/girija/fpga/bcd_cntr/bcd_cntr.vhd.
    Found 4-bit register for signal <count>.
    Found 4-bit register for signal <count1>.
    Found 8-bit adder for signal <$n0000> created at line 61.
    Found 4-bit adder for signal <$n0001> created at line 64.
    Found 8-bit comparator lessequal for signal <$n0018> created at line 66.
    Found 8-bit comparator greatequal for signal <$n0027> created at line 62.
    Found 8-bit register for signal <cnt1>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   2 Comparator(s).
Unit <bcd_cntr> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 8-bit adder                       : 1
 4-bit adder                       : 1
# Counters                         : 4
 8-bit up counter                  : 3
 3-bit up counter                  : 1
# Registers                        : 20
 1-bit register                    : 18
 4-bit register                    : 2
# Comparators                      : 3
 8-bit comparator greatequal       : 1
 8-bit comparator lessequal        : 1
 3-bit comparator less             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <bcd_cntr> ...

Optimizing unit <testcnt> ...
Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block bcd_cntr, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                      44  out of    768     5%  
 Number of Slice Flip Flops:            53  out of   1536     3%  
 Number of 4 input LUTs:                62  out of   1536     4%  
 Number of bonded IOBs:                  9  out of    124     7%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u4_t:Q                             | NONE                   | 16    |
u3_one:Q                           | NONE                   | 4     |
u3_check:Q                         | NONE                   | 2     |
u2_one:Q                           | NONE                   | 9     |
u2_check:Q                         | NONE                   | 2     |
u1_one:Q                           | NONE                   | 9     |
u1_check:Q                         | NONE                   | 2     |
clk                                | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.183ns (Maximum Frequency: 239.063MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.106ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_cntr/_ngo -i -p
xc3s50-pq208-5 bcd_cntr.ngc bcd_cntr.ngd 

Reading NGO file "g:/girija/fpga/bcd_cntr/bcd_cntr.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36040 kilobytes

Writing NGD file "bcd_cntr.ngd" ...

Writing NGDBUILD log file "bcd_cntr.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\girija\fpga\bcd_cntr/_ngo -uc
bcd_cntr.ucf -p xc3s50-pq208-5 bcd_cntr.ngc bcd_cntr.ngd 

Reading NGO file "g:/girija/fpga/bcd_cntr/bcd_cntr.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "bcd_cntr.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38088 kilobytes

Writing NGD file "bcd_cntr.ngd" ...

Writing NGDBUILD log file "bcd_cntr.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s50pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          45 out of   1,536    2%
  Number of 4 input LUTs:              29 out of   1,536    1%
Logic Distribution:
  Number of occupied Slices:                           41 out of     768    5%
    Number of Slices containing only related logic:      41 out of      41  100%
    Number of Slices containing unrelated logic:          0 out of      41    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:             57 out of   1,536    3%
  Number used as logic:                 29
  Number used as a route-thru:          28
  Number of bonded IOBs:               10 out of     124    8%
    IOB Flip Flops:                     8
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  769
Additional JTAG gate count for IOBs:  480
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "bcd_cntr_map.mrp" for details.
Completed process "Map".

Mapping Module bcd_cntr . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o bcd_cntr_map.ncd bcd_cntr.ngd bcd_cntr.pcf
Mapping Module bcd_cntr: DONE



Started process "Place & Route".





Constraints file: bcd_cntr.pcf

Loading device database for application Par from file "bcd_cntr_map.ncd".
   "bcd_cntr" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            10 out of 124     8%
      Number of LOCed External IOBs   10 out of 10    100%

   Number of Slices                   41 out of 768     5%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98971f) REAL time: 3 secs 

.
Phase 3.8
.
Phase 3.8 (Checksum:98b8c6) REAL time: 3 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 3 secs 

Writing design to file bcd_cntr.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 234 unrouted;       REAL time: 3 secs 

Phase 2: 201 unrouted;       REAL time: 3 secs 

Phase 3: 40 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX0| No   |    5 |  0.000     |  0.868      |
+-------------------------+----------+------+------+------------+-------------+
|            u1_one       |   Local  |      |    5 |  0.900     |  1.534      |
+-------------------------+----------+------+------+------------+-------------+
|            u2_one       |   Local  |      |    5 |  0.629     |  1.388      |
+-------------------------+----------+------+------+------------+-------------+
|              u4_t       |   Local  |      |   15 |  1.434     |  2.264      |
+-------------------------+----------+------+------+------------+-------------+
|            u3_one       |   Local  |      |    3 |  0.008     |  1.144      |
+-------------------------+----------+------+------+------------+-------------+
|          u2_check       |   Local  |      |    3 |  0.000     |  1.597      |
+-------------------------+----------+------+------+------------+-------------+
|          u1_check       |   Local  |      |    3 |  0.000     |  1.199      |
+-------------------------+----------+------+------+------------+-------------+
|          u3_check       |   Local  |      |    3 |  0.000     |  1.549      |
+-------------------------+----------+------+------+------------+-------------+