bcd_cntr.syr

this program give the functionality bcd count

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : bcd_cntr.ngr
Top Level Output File Name         : bcd_cntr
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 12

Macro Statistics :
# Registers                        : 13
#      1-bit register              : 10
#      20-bit register             : 1
#      4-bit register              : 2
# Adders/Subtractors               : 2
#      20-bit adder                : 1
#      8-bit adder                 : 1
# Comparators                      : 4
#      20-bit comparator less      : 1
#      8-bit comparator greatequal : 1
#      8-bit comparator greater    : 1
#      8-bit comparator lessequal  : 1

Cell Usage :
# BELS                             : 117
#      GND                         : 1
#      LUT1                        : 15
#      LUT1_D                      : 1
#      LUT1_L                      : 18
#      LUT2                        : 2
#      LUT2_L                      : 3
#      LUT3                        : 1
#      LUT3_L                      : 6
#      LUT4                        : 3
#      LUT4_L                      : 5
#      MUXCY                       : 35
#      VCC                         : 1
#      XORCY                       : 26
# FlipFlops/Latches                : 37
#      FDCE                        : 16
#      FDE                         : 1
#      FDR                         : 20
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 11
#      IBUF                        : 2
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                      37  out of    768     4%  
 Number of Slice Flip Flops:            37  out of   1536     2%  
 Number of 4 input LUTs:                54  out of   1536     3%  
 Number of bonded IOBs:                 11  out of    124     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u2_fiftyhz:Q                       | NONE                   | 16    |
clk                                | BUFGP                  | 21    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 4.928ns (Maximum Frequency: 202.922MHz)
   Minimum input arrival time before clock: 3.894ns
   Maximum output required time after clock: 5.106ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'u2_fiftyhz:Q'
Delay:               4.928ns (Levels of Logic = 3)
  Source:            cnt1_4 (FF)
  Destination:       count_2 (FF)
  Source Clock:      u2_fiftyhz:Q rising
  Destination Clock: u2_fiftyhz:Q rising

  Data Path: cnt1_4 to count_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             7   0.626   0.717  cnt1_4 (cnt1_4)
     LUT4_L:I2->LO         1   0.479   0.100  _n00291_SW0 (N1782)
     LUT4:I3->O            9   0.479   0.777  _n00291 (_n0029)
     LUT2:I0->O            8   0.479   0.747  _n00401 (_n0040)
     FDCE:CE                   0.524          count_1
    ----------------------------------------
    Total                      4.928ns (2.587ns logic, 2.341ns route)
                                       (52.5% logic, 47.5% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               4.703ns (Levels of Logic = 10)
  Source:            u2_temp_100000_4 (FF)
  Destination:       u2_temp_100000_19 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u2_temp_100000_4 to u2_temp_100000_19
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   0.465  u2_temp_100000_4 (u2_temp_100000_4)
     LUT2_L:I0->LO         1   0.479   0.000  u2_Andlut (u2_N646)
     MUXCY:S->O            1   0.435   0.000  u2_Andcy (u2_And_cyo)
     MUXCY:CI->O           1   0.056   0.000  u2_norcy (u2_nor_cyo)
     MUXCY:CI->O           1   0.056   0.000  u2_Andcy_rn_0 (u2_And_cyo1)
     MUXCY:CI->O           1   0.056   0.000  u2_norcy_rn_0 (u2_nor_cyo1)
     MUXCY:CI->O           1   0.056   0.000  u2_Andcy_rn_1 (u2_And_cyo2)
     MUXCY:CI->O           1   0.056   0.000  u2_norcy_rn_1 (u2_nor_cyo2)
     MUXCY:CI->O           1   0.056   0.000  u2_Andcy_rn_2 (u2_And_cyo3)
     MUXCY:CI->O           1   0.056   0.000  u2_norcy_rn_2 (u2_nor_cyo3)
     MUXCY:CI->O          21   0.246   1.172  u2_Andcy_rn_3 (u2_And_cyo4)
     FDR:R                     0.892          u2_temp_100000_0
    ----------------------------------------
    Total                      4.703ns (3.066ns logic, 1.637ns route)
                                       (65.2% logic, 34.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u2_fiftyhz:Q'
Offset:              3.894ns (Levels of Logic = 2)
  Source:            pulse (PAD)
  Destination:       count_2 (FF)
  Destination Clock: u2_fiftyhz:Q rising

  Data Path: pulse to count_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   1.679   0.465  u1 (bpulse)
     LUT1:I0->O            8   0.479   0.747  cnt1_3_N1521 (cnt1_3_N152)
     FDCE:CE                   0.524          cnt1_3
    ----------------------------------------
    Total                      3.894ns (2.682ns logic, 1.212ns route)
                                       (68.9% logic, 31.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'u2_fiftyhz:Q'
Offset:              5.106ns (Levels of Logic = 1)
  Source:            count1_3 (FF)
  Destination:       count1<3> (PAD)
  Source Clock:      u2_fiftyhz:Q rising

  Data Path: count1_3 to count1<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.626   0.240  count1_3 (count1_3)
     OBUF:I->O                 4.240          count1_3_OBUF (count1<3>)
    ----------------------------------------
    Total                      5.106ns (4.866ns logic, 0.240ns route)
                                       (95.3% logic, 4.7% route)

=========================================================================
CPU : 11.52 / 13.11 s | Elapsed : 12.00 / 13.00 s
 
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Total memory usage is 64760 kilobytes