bcd_cntr.syr

this program give the functionality bcd count

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: bcd_cntr.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : bcd_cntr.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : bcd_cntr
Output Format                      : NGC
Target Device                      : xc3s50-5-pq208

---- Source Options
Top Module Name                    : bcd_cntr
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : bcd_cntr.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/GIRIJA/FPGApgms/bcd_cntr/dvd100k.vhd in Library work.
Architecture behavioral of Entity dvd100k is up to date.
Compiling vhdl file G:/GIRIJA/FPGApgms/bcd_cntr/bcd_cntr.vhd in Library work.
Architecture behavioral of Entity bcd_cntr is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <bcd_cntr> (Architecture <behavioral>).
WARNING:Xst:766 - G:/GIRIJA/FPGApgms/bcd_cntr/bcd_cntr.vhd line 46: Generating a Black Box for component <ibuf>.
Entity <bcd_cntr> analyzed. Unit <bcd_cntr> generated.

Analyzing Entity <dvd100k> (Architecture <behavioral>).
Entity <dvd100k> analyzed. Unit <dvd100k> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dvd100k>.
    Related source file is G:/GIRIJA/FPGApgms/bcd_cntr/dvd100k.vhd.
    Found 20-bit comparator less for signal <$n0003> created at line 21.
    Found 1-bit register for signal <fiftyhz>.
    Found 20-bit up counter for signal <temp_100000>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <dvd100k> synthesized.


Synthesizing Unit <bcd_cntr>.
    Related source file is G:/GIRIJA/FPGApgms/bcd_cntr/bcd_cntr.vhd.
WARNING:Xst:653 - Signal <rowtemp> is used but never assigned. Tied to value 0.
    Found 1-bit register for signal <row>.
    Found 4-bit register for signal <count>.
    Found 4-bit register for signal <count1>.
    Found 8-bit adder for signal <$n0000> created at line 61.
    Found 4-bit adder for signal <$n0001> created at line 65.
    Found 8-bit comparator lessequal for signal <$n0029> created at line 67.
    Found 8-bit comparator greatequal for signal <$n0030> created at line 63.
    Found 8-bit comparator greater for signal <$n0032> created at line 67.
    Found 8-bit register for signal <cnt1>.
    Summary:
	inferred  17 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <bcd_cntr> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 8-bit adder                       : 1
 4-bit adder                       : 1
# Counters                         : 1
 20-bit up counter                 : 1
# Registers                        : 12
 1-bit register                    : 10
 4-bit register                    : 2
# Comparators                      : 4
 8-bit comparator greater          : 1
 8-bit comparator greatequal       : 1
 8-bit comparator lessequal        : 1
 20-bit comparator less            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <row> (without init value) is constant in block <bcd_cntr>.
WARNING:Xst:1988 - Unit <bcd_cntr>: instances <Mcompar__n0029>, <Mcompar__n0032> of unit <LPM_COMPARE_2> and unit <LPM_COMPARE_4> are dual, second instance is removed

Optimizing unit <bcd_cntr> ...

Optimizing unit <dvd100k> ...
Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block bcd_cntr, actual ratio is 4.