bcd_cntr.vhd

this program give the functionality bcd count

  --bcd_counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;
--rst is the reset switch i/p
--count1 is 4bit LSB o/p
--count is 4bit MSB o/p
--pulse is the pushbotton i/p
entity bcd_cntr is
Port ( pulse : in std_logic;
       	rst : in std_logic;
	   	row :out std_logic;
		 clk:in std_logic;
        count : out std_logic_vector(3 downto 0);
	  count1 : out std_logic_vector(3 downto 0));
		 
end bcd_cntr;

architecture Behavioral of bcd_cntr is
--locally used signals
	  signal rowtemp: std_logic:='0';
       signal bpulse:std_logic;
	  signal cnt1: std_logic_vector(7 downto 0):="00000000";
	  signal bclk:std_logic ;
	  

--sub component declaration  of divide by 100k counter
	component dvd100k is
    Port (  clkin : in std_logic;
           clkout : out std_logic);
	 end component;
   component ibuf
	port( i: in std_logic;
           o: out std_logic);
	end component;

--component instantiation
--port mapping of ibuf
begin
u1: ibuf port map( i => pulse, o => bpulse);
--port mapping of divide by 100k counter
u2:dvd100k	port map( clkin => clk, clkout => bclk);  --10Mhz/1000000 = 10hz
--port mapping of testcount

process(rst,bpulse,bclk)
begin
	if rst='1' then
			 count1<="0000";
			 count<="0000";
			 cnt1<="00000000";
 elsif bclk'event and bclk='1'then
       if bpulse='0' then
           row <= rowtemp;
		    if rowtemp = '0' then
			     cnt1 <= cnt1 + '1';
			if cnt1(3 downto 0)>= "00001001"	then
				 cnt1(3 downto 0)<= "0000"	;
			 	 cnt1(7 downto 4) <= cnt1(7 downto 4) + '1';	
			end if;
	      	if cnt1<="10011001" then
			count1 <= cnt1(3 downto 0);
			count <= cnt1(7 downto 4);
			else
				  cnt1<= "00000000";
			end if;
		end if;	 
	end if;
end if;
end process;
end behavioral;