📄 dvd100k.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dvd100k is
Port ( clkin : in std_logic; --10Mhz clock i/p
clkout:out std_logic); --clock output 10hz
end dvd100k;
architecture Behavioral of dvd100k is
signal temp_100000:std_logic_vector(19 downto 0):="11111111111111111111";--internal signal to count 1000000 counts
signal fiftyhz:std_logic:='1';
begin
clkout <=fiftyhz; --i.e 1000000 counts ON period and 1000000 coounts OFF period
process(clkin)
begin
if clkin'event and clkin = '1' then
if temp_100000 < "10110111000110110000" then --to generate 50hz clock, counts upto 1000000 counts
temp_100000 <= temp_100000 + '1' ; --1000000 counts ON period and 1000000 counts OFF period
else
fiftyhz <= not fiftyhz; --complimenting signal clkout for each 10000000 clocks
temp_100000 <= "00000000000000000000" ;
end if;
end if;
end process ;
end Behavioral;
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