bcd_cntr.par

this program give the functionality bcd count

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

P4::  Sat Jan 21 14:49:09 2006


E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 bcd_cntr_map.ncd
bcd_cntr.ncd bcd_cntr.pcf 


Constraints file: bcd_cntr.pcf

Loading device database for application Par from file "bcd_cntr_map.ncd".
   "bcd_cntr" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolved that IOB <clk> must be placed at site P79.
Resolved that IOB <count<0>> must be placed at site P34.
Resolved that IOB <count<1>> must be placed at site P28.
Resolved that IOB <count<2>> must be placed at site P26.
Resolved that IOB <count<3>> must be placed at site P20.
Resolved that IOB <pulse> must be placed at site P143.
Resolved that IOB <count1<0>> must be placed at site P44.
Resolved that IOB <count1<1>> must be placed at site P42.
Resolved that IOB <count1<2>> must be placed at site P39.
Resolved that IOB <count1<3>> must be placed at site P36.
Resolved that IOB <row> must be placed at site P138.
Resolved that IOB <rst> must be placed at site P21.


Device utilization summary:

   Number of External IOBs            12 out of 124     9%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of Slices                   28 out of 768     3%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989715) REAL time: 0 secs 

.
Phase 3.8
.
Phase 3.8 (Checksum:98bbf0) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file bcd_cntr.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 190 unrouted;       REAL time: 0 secs 

Phase 2: 161 unrouted;       REAL time: 0 secs 

Phase 3: 29 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX0| No   |   11 |  0.000     |  0.868      |
+-------------------------+----------+------+------+------------+-------------+
|        u2_fiftyhz       |   Local  |      |   15 |  0.594     |  1.920      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 103


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.749
   The MAXIMUM PIN DELAY IS:                               3.480
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.424

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         145          38           4           3           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file bcd_cntr.ncd.


PAR done.