📄 alu_2bit.twr
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Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
E:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml alu_2bit alu_2bit.ncd -o
alu_2bit.twr alu_2bit.pcf
Design file: alu_2bit.ncd
Physical constraint file: alu_2bit.pcf
Device,speed: xc3s50,-5 (ADVANCED 1.32 2004-06-25)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk1
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
ce | 3.444(R)| -1.451(R)|clk1_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Setup/Hold to clock m
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
ain<0> | 2.912(R)| 3.006(R)|m_BUFGP | 0.000|
| -0.294(F)| 2.882(F)|m_BUFGP | 0.000|
ain<1> | 2.450(R)| 2.938(R)|m_BUFGP | 0.000|
| -0.437(F)| 3.021(F)|m_BUFGP | 0.000|
bin<0> | 3.277(R)| 2.496(R)|m_BUFGP | 0.000|
| 0.192(F)| 2.493(F)|m_BUFGP | 0.000|
bin<1> | 3.828(R)| 2.131(R)|m_BUFGP | 0.000|
| 0.019(F)| 2.656(F)|m_BUFGP | 0.000|
cin | 2.369(R)| 3.212(R)|m_BUFGP | 0.000|
sel | 1.811(R)| 2.500(R)|m_BUFGP | 0.000|
| 0.379(F)| 2.446(F)|m_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock m to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
sout<0> | 9.340(F)|m_BUFGP | 0.000|
sout<1> | 9.340(F)|m_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk1
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk1 | 3.866| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock m
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
m | 4.610| | | 1.827|
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
ain<0> |cout | 9.039|
ain<1> |cout | 8.293|
bin<0> |cout | 9.603|
bin<1> |cout | 8.920|
cin |cout | 8.721|
---------------+---------------+---------+
Analysis completed Sat Feb 18 09:24:09 2006
--------------------------------------------------------------------------------
Peak Memory Usage: 46 MB
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