__projnav.log

this programs gives the functionality of 2bit alu

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.802ns (Maximum Frequency: 356.888MHz)
   Minimum input arrival time before clock: 4.774ns
   Maximum output required time after clock: 6.275ns
   Maximum combinational path delay: 8.359ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\vijay_fpga_lab\alu_2bit/_ngo -uc
alu_2bit.ucf -p xc3s50-pq208-5 alu_2bit.ngc alu_2bit.ngd 

Reading NGO file "G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "alu_2bit.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38148 kilobytes

Writing NGD file "alu_2bit.ngd" ...

Writing NGDBUILD log file "alu_2bit.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s50pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Total Number Slice Registers:        30 out of   1,536    1%
    Number used as Flip Flops:                    14
    Number used as Latches:                       16
  Number of 4 input LUTs:              61 out of   1,536    3%
Logic Distribution:
  Number of occupied Slices:                           36 out of     768    4%
    Number of Slices containing only related logic:      36 out of      36  100%
    Number of Slices containing unrelated logic:          0 out of      36    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          61 out of   1,536    3%
  Number of bonded IOBs:               24 out of     124   19%
    IOB Latches:                       10
  Number of GCLKs:                     2 out of       8   25%

Total equivalent gate count for design:  620
Additional JTAG gate count for IOBs:  1,152
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "alu_2bit_map.mrp" for details.
Completed process "Map".

Mapping Module alu_2bit . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o alu_2bit_map.ncd alu_2bit.ngd alu_2bit.pcf
Mapping Module alu_2bit: DONE



Started process "Place & Route".





Constraints file: alu_2bit.pcf

Loading device database for application Par from file "alu_2bit_map.ncd".
   "alu_2bit" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            24 out of 124    19%
      Number of LOCed External IOBs   24 out of 24    100%

   Number of Slices                   36 out of 768     4%

   Number of BUFGMUXs                  2 out of 8      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989739) REAL time: 0 secs 

......
.........
Phase 3.8
.
Phase 3.8 (Checksum:98da59) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file alu_2bit.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 258 unrouted;       REAL time: 2 secs 

Phase 2: 228 unrouted;       REAL time: 2 secs 

Phase 3: 73 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|           m_BUFGP       |  BUFGMUX7| No   |   12 |  0.035     |  0.903      |
+-------------------------+----------+------+------+------------+-------------+
|        clk1_BUFGP       |  BUFGMUX0| No   |    4 |  0.000     |  0.868      |
+-------------------------+----------+------+------+------------+-------------+
|      u4_u1_dout_1       |   Local  |      |   33 |  0.854     |  1.680      |
+-------------------------+----------+------+------+------------+-------------+
|           u1_temp       |   Local  |      |    5 |  0.000     |  1.659      |
+-------------------------+----------+------+------+------------+-------------+
|           u2_temp       |   Local  |      |    3 |  0.000     |  1.209      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file alu_2bit.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Tue Feb 14 14:49:50 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module alu_2bit . . .
PAR command line: par -w -intstyle ise -ol std -t 1 alu_2bit_map.ncd alu_2bit.ncd alu_2bit.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.
Entity <alu_2bit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu_2bit> (Architecture <behavioral>).
WARNING:Xst:819 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 93: The following signals are missing in the process sensitivity list:
   tempcout, tempdis.
WARNING:Xst:1610 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 121: Width mismatch. <dtemp> has a width of 4 bits but assigned expression is 2-bit wide.
WARNING:Xst:1610 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 127: Width mismatch. <dtemp1> has a width of 4 bits but assigned expression is 2-bit wide.
WARNING:Xst:819 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 114: The following signals are missing in the process sensitivity list:
   ain, bin.
Entity <alu_2bit> analyzed. Unit <alu_2bit> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <dflip> (Architecture <behavioral>).
Entity <dflip> analyzed. Unit <dflip> generated.

Analyzing Entity <dflipflop> (Architecture <behavioral>).
Entity <dflipflop> analyzed. Unit <dflipflop> generated.

Analyzing Entity <invtr> (Architecture <behavioral>).
Entity <invtr> analyzed. Unit <invtr> generated.

Analyzing Entity <buff> (Architecture <behavioral>).
Entity <buff> analyzed. Unit <buff> generated.

Analyzing Entity <fbitaddr> (Architecture <behavioral>).
Entity <fbitaddr> analyzed. Unit <fbitaddr> generated.

Analyzing Entity <fulladdr> (Architecture <behavioral>).
Entity <fulladdr> analyzed. Unit <fulladdr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fulladdr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd.
Unit <fulladdr> synthesized.


Synthesizing Unit <buff>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/buff.vhd.
Unit <buff> synthesized.


Synthesizing Unit <invtr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd.
Unit <invtr> synthesized.


Synthesizing Unit <dflipflop>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd.
    Found 1-bit register for signal <dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <dflipflop> synthesized.


Synthesizing Unit <fbitaddr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd.
WARNING:Xst:1305 - Output <s4<3:2>> is never assigned. Tied to value 00.
WARNING:Xst:1780 - Signal <c3> is never used or assigned.
WARNING:Xst:1780 - Signal <c4> is never used or assigned.
Unit <fbitaddr> synthesized.


Synthesizing Unit <dflip>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd.
WARNING:Xst:1780 - Signal <temp2> is never used or assigned.
Unit <dflip> synthesized.


Synthesizing Unit <testcnt>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd.
    Found 5-bit comparator less for signal <$n0004> created at line 25.
    Found 5-bit adder for signal <$n0005> created at line 26.
    Found 5-bit register for signal <cnt>.
    Found 1-bit register for signal <temp>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <testcnt> synthesized.


Synthesizing Unit <alu_2bit>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd.
WARNING:Xst:646 - Signal <tempsout> is assigned