__projnav.log

this programs gives the functionality of 2bit alu

E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            24 out of 124    19%
      Number of LOCed External IOBs   24 out of 24    100%

   Number of Slices                   30 out of 768     3%

   Number of BUFGMUXs                  2 out of 8      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989727) REAL time: 2 secs 

......
.........
Phase 3.8
.
Phase 3.8 (Checksum:98d0db) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file alu_2bit.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 229 unrouted;       REAL time: 2 secs 

Phase 2: 198 unrouted;       REAL time: 3 secs 

Phase 3: 69 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 

Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|           m_BUFGP       |  BUFGMUX7| No   |    8 |  0.035     |  0.903      |
+-------------------------+----------+------+------+------------+-------------+
|        clk1_BUFGP       |  BUFGMUX0| No   |    4 |  0.000     |  0.868      |
+-------------------------+----------+------+------+------------+-------------+
|      u4_u1_dout_1       |   Local  |      |   31 |  0.015     |  1.783      |
+-------------------------+----------+------+------+------------+-------------+
|           u1_temp       |   Local  |      |    5 |  0.000     |  1.659      |
+-------------------------+----------+------+------+------------+-------------+
|           u2_temp       |   Local  |      |    3 |  0.006     |  1.623      |
+-------------------------+----------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  51 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file alu_2bit.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Tue Feb 14 14:06:59 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module alu_2bit . . .
PAR command line: par -w -intstyle ise -ol std -t 1 alu_2bit_map.ncd alu_2bit.ncd alu_2bit.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------



Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.
Entity <alu_2bit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu_2bit> (Architecture <behavioral>).
WARNING:Xst:819 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 93: The following signals are missing in the process sensitivity list:
   tempcout, tempdis.
WARNING:Xst:1610 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 121: Width mismatch. <dtemp> has a width of 4 bits but assigned expression is 2-bit wide.
WARNING:Xst:1610 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 127: Width mismatch. <dtemp1> has a width of 4 bits but assigned expression is 2-bit wide.
WARNING:Xst:819 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 114: The following signals are missing in the process sensitivity list:
   ain, bin.
Entity <alu_2bit> analyzed. Unit <alu_2bit> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <dflip> (Architecture <behavioral>).
Entity <dflip> analyzed. Unit <dflip> generated.

Analyzing Entity <dflipflop> (Architecture <behavioral>).
Entity <dflipflop> analyzed. Unit <dflipflop> generated.

Analyzing Entity <invtr> (Architecture <behavioral>).
Entity <invtr> analyzed. Unit <invtr> generated.

Analyzing Entity <buff> (Architecture <behavioral>).
Entity <buff> analyzed. Unit <buff> generated.

Analyzing Entity <fbitaddr> (Architecture <behavioral>).
Entity <fbitaddr> analyzed. Unit <fbitaddr> generated.

Analyzing Entity <fulladdr> (Architecture <behavioral>).
Entity <fulladdr> analyzed. Unit <fulladdr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fulladdr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd.
Unit <fulladdr> synthesized.


Synthesizing Unit <buff>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/buff.vhd.
Unit <buff> synthesized.


Synthesizing Unit <invtr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd.
Unit <invtr> synthesized.


Synthesizing Unit <dflipflop>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd.
    Found 1-bit register for signal <dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <dflipflop> synthesized.


Synthesizing Unit <fbitaddr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd.
WARNING:Xst:1305 - Output <s4<3:2>> is never assigned. Tied to value 00.
WARNING:Xst:1780 - Signal <c3> is never used or assigned.
WARNING:Xst:1780 - Signal <c4> is never used or assigned.
Unit <fbitaddr> synthesized.


Synthesizing Unit <dflip>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd.
WARNING:Xst:1780 - Signal <temp2> is never used or assigned.
Unit <dflip> synthesized.


Synthesizing Unit <testcnt>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd.
    Found 5-bit comparator less for signal <$n0004> created at line 25.
    Found 5-bit adder for signal <$n0005> created at line 26.
    Found 5-bit register for signal <cnt>.
    Found 1-bit register for signal <temp>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <testcnt> synthesized.


Synthesizing Unit <alu_2bit>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd.
WARNING:Xst:646 - Signal <tempsout> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <dis_out>.
WARNING:Xst:737 - Found 4-bit latch for signal <dtemp>.
WARNING:Xst:737 - Found 8-bit latch for signal <tempdis>.
WARNING:Xst:737 - Found 4-bit latch for signal <dtemp1>.
WARNING:Xst:737 - Found 2-bit latch for signal <stemp1>.
WARNING:Xst:737 - Found 2-bit latch for signal <stemp>.
    Found 16x8-bit ROM for signal <temp_out>.
    Found 2-bit subtractor for signal <$n0002> created at line 121.
    Found 2-bit adder for signal <$n0007> created at line 127.
    Found 17 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Adder/Subtracter(s).
	inferred  17 Multiplexer(s).
Unit <alu_2bit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 4
 2-bit adder                       : 1
 2-bit subtractor                  : 1
 5-bit adder                       : 2
# Registers                        : 6
 1-bit register                    : 4
 5-bit register                    : 2
# Latches                          : 6
 2-bit latch                       : 2
 4-bit latch                       : 2
 8-bit latch                       : 2
# Comparators                      : 2
 5-bit comparator less             : 2
# Multiplexers                     : 5
 8-bit 2-to-1 multiplexer          : 1
 1-bit 2-to-1 multiplexer          : 1
 2-bit 2-to-1 multiplexer          : 2
 4-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <dflip>: instances <u1>, <XLXI_6> of unit <dflipflop> are equivalent, second instance is removed
WARNING:Xst:1710 - FF/Latch  <dtemp1_3> (without init value) is constant in block <alu_2bit>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <dtemp1_2> (without init value) is constant in block <alu_2bit>.

Optimizing unit <alu_2bit> ...

Optimizing unit <fulladdr> ...

Optimizing unit <testcnt> ...
Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block alu_2bit, actual ratio is 4.
WARNING:Xst:1426 - The value init of the FF/Latch tempdis_7 hinder the constant cleaning in the block alu_2bit.
   You should achieve better results by setting this init to 1.
FlipFlop u4_u1_dout has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                      39  out of    768     5%  
 Number of Slice Flip Flops:            40  out of   1536     2%  
 Number of 4 input LUTs:                67  out of   1536     4%  
 Number of bonded IOBs:                 22  out of    124    17%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
u2_temp:Q                          | NONE                   | 2     |
clk1                               | BUFGP                  | 6     |
u1_temp:Q                          | NONE                   | 6     |
m                                  | BUFGP                  | 18    |
u4_u1_dout_1:Q                     | NONE                   | 8     |
-----------------------------------+------------------------+-------+