__projnav.log

this programs gives the functionality of 2bit alu

Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.
Entity <alu_2bit> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu_2bit> (Architecture <Behavioral>).
WARNING:Xst:819 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 91: The following signals are missing in the process sensitivity list:
   tempcout, tempdis.
WARNING:Xst:1610 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 119: Width mismatch. <dtemp> has a width of 4 bits but assigned expression is 2-bit wide.
WARNING:Xst:1610 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 125: Width mismatch. <dtemp> has a width of 4 bits but assigned expression is 2-bit wide.
WARNING:Xst:819 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd line 112: The following signals are missing in the process sensitivity list:
   ain, bin.
Entity <alu_2bit> analyzed. Unit <alu_2bit> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <dflip> (Architecture <behavioral>).
Entity <dflip> analyzed. Unit <dflip> generated.

Analyzing Entity <dflipflop> (Architecture <behavioral>).
Entity <dflipflop> analyzed. Unit <dflipflop> generated.

Analyzing Entity <invtr> (Architecture <behavioral>).
Entity <invtr> analyzed. Unit <invtr> generated.

Analyzing Entity <buff> (Architecture <behavioral>).
Entity <buff> analyzed. Unit <buff> generated.

Analyzing Entity <fbitaddr> (Architecture <behavioral>).
Entity <fbitaddr> analyzed. Unit <fbitaddr> generated.

Analyzing Entity <fulladdr> (Architecture <behavioral>).
Entity <fulladdr> analyzed. Unit <fulladdr> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fulladdr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd.
Unit <fulladdr> synthesized.


Synthesizing Unit <buff>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/buff.vhd.
Unit <buff> synthesized.


Synthesizing Unit <invtr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd.
Unit <invtr> synthesized.


Synthesizing Unit <dflipflop>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd.
    Found 1-bit register for signal <dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <dflipflop> synthesized.


Synthesizing Unit <fbitaddr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd.
WARNING:Xst:1305 - Output <s4<3:2>> is never assigned. Tied to value 00.
WARNING:Xst:1780 - Signal <c3> is never used or assigned.
WARNING:Xst:1780 - Signal <c4> is never used or assigned.
Unit <fbitaddr> synthesized.


Synthesizing Unit <dflip>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd.
WARNING:Xst:1780 - Signal <temp2> is never used or assigned.
Unit <dflip> synthesized.


Synthesizing Unit <testcnt>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd.
    Found 5-bit comparator less for signal <$n0004> created at line 25.
    Found 5-bit adder for signal <$n0005> created at line 26.
    Found 5-bit register for signal <cnt>.
    Found 1-bit register for signal <temp>.
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <testcnt> synthesized.


Synthesizing Unit <alu_2bit>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd.
WARNING:Xst:646 - Signal <tempsout> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <dis_out>.
WARNING:Xst:737 - Found 4-bit latch for signal <dtemp>.
WARNING:Xst:737 - Found 8-bit latch for signal <tempdis>.
WARNING:Xst:737 - Found 2-bit latch for signal <stemp>.
    Found 16x8-bit ROM for signal <temp_out>.
    Found 2-bit adder for signal <$n0002> created at line 119.
    Found 2-bit adder for signal <$n0004> created at line 125.
    Found 11 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Adder/Subtracter(s).
	inferred  11 Multiplexer(s).
Unit <alu_2bit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Adders/Subtractors               : 4
 2-bit adder                       : 2
 5-bit adder                       : 2
# Registers                        : 6
 1-bit register                    : 4
 5-bit register                    : 2
# Latches                          : 4
 2-bit latch                       : 1
 8-bit latch                       : 2
 4-bit latch                       : 1
# Comparators                      : 2
 5-bit comparator less             : 2
# Multiplexers                     : 3
 8-bit 2-to-1 multiplexer          : 1
 1-bit 2-to-1 multiplexer          : 1
 2-bit 2-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <dflip>: instances <u1>, <XLXI_6> of unit <dflipflop> are equivalent, second instance is removed
WARNING:Xst:1710 - FF/Latch  <tempdis_1> (without init value) is constant in block <alu_2bit>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <dtemp_3> (without init value) is constant in block <alu_2bit>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <dtemp_2> (without init value) is constant in block <alu_2bit>.

Optimizing unit <alu_2bit> ...

Optimizing unit <fulladdr> ...

Optimizing unit <testcnt> ...
Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block alu_2bit, actual ratio is 4.
FlipFlop u4_u1_dout has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                      32  out of    768     4%  
 Number of Slice Flip Flops:            33  out of   1536     2%  
 Number of 4 input LUTs:                57  out of   1536     3%  
 Number of bonded IOBs:                 22  out of    124    17%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk1                               | BUFGP                  | 6     |
u2_temp:Q                          | NONE                   | 2     |
u1_temp:Q                          | NONE                   | 6     |
m                                  | BUFGP                  | 11    |
u4_u1_dout_1:Q                     | NONE                   | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.802ns (Maximum Frequency: 356.888MHz)
   Minimum input arrival time before clock: 4.803ns
   Maximum output required time after clock: 6.387ns
   Maximum combinational path delay: 8.388ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\vijay_fpga_lab\alu_2bit/_ngo -i -p
xc3s50-pq208-5 alu_2bit.ngc alu_2bit.ngd 

Reading NGO file "G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 36100 kilobytes

Writing NGD file "alu_2bit.ngd" ...

Writing NGDBUILD log file "alu_2bit.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\vijay_fpga_lab\alu_2bit/_ngo -uc
alu_2bit.ucf -p xc3s50-pq208-5 alu_2bit.ngc alu_2bit.ngd 

Reading NGO file "G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "alu_2bit.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38148 kilobytes

Writing NGD file "alu_2bit.ngd" ...

Writing NGDBUILD log file "alu_2bit.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "3s50pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Total Number Slice Registers:        23 out of   1,536    1%
    Number used as Flip Flops:                    14
    Number used as Latches:                        9
  Number of 4 input LUTs:              53 out of   1,536    3%
Logic Distribution:
  Number of occupied Slices:                           30 out of     768    3%
    Number of Slices containing only related logic:      30 out of      30  100%
    Number of Slices containing unrelated logic:          0 out of      30    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          53 out of   1,536    3%
  Number of bonded IOBs:               24 out of     124   19%
    IOB Latches:                       10
  Number of GCLKs:                     2 out of       8   25%

Total equivalent gate count for design:  534
Additional JTAG gate count for IOBs:  1,152
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "alu_2bit_map.mrp" for details.
Completed process "Map".

Mapping Module alu_2bit . . .
MAP command line:
map -intstyle ise -p xc3s50-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o alu_2bit_map.ncd alu_2bit.ngd alu_2bit.pcf
Mapping Module alu_2bit: DONE



Started process "Place & Route".





Constraints file: alu_2bit.pcf

Loading device database for application Par from file "alu_2bit_map.ncd".
   "alu_2bit" is an NCD, version 2.38, device xc3s50, package pq208, speed -5
Loading device for application Par from file '3s50.nph' in environment