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this programs gives the functionality of 2bit alu

=========================================================================
Analyzing Entity <dflip> (Architecture <behavioral>).
ERROR:Xst:761 - G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd line 56: No default binding for component: <buff>. Ports <I,O> do not match.
--> 

Total memory usage is 51448 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Entity <buff> (Architecture <behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dflip> (Architecture <behavioral>).
ERROR:Xst:761 - G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd line 56: No default binding for component: <buff>. Ports <I,O> do not match.
--> 

Total memory usage is 51448 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Entity <buff> (Architecture <behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Entity <dflip> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dflip> (Architecture <behavioral>).
Entity <dflip> analyzed. Unit <dflip> generated.

Analyzing Entity <dflipflop> (Architecture <behavioral>).
Entity <dflipflop> analyzed. Unit <dflipflop> generated.

Analyzing Entity <invtr> (Architecture <behavioral>).
Entity <invtr> analyzed. Unit <invtr> generated.

Analyzing Entity <buff> (Architecture <behavioral>).
Entity <buff> analyzed. Unit <buff> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <buff>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/buff.vhd.
Unit <buff> synthesized.


Synthesizing Unit <invtr>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd.
Unit <invtr> synthesized.


Synthesizing Unit <dflipflop>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd.
    Found 1-bit register for signal <dout>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <dflipflop> synthesized.


Synthesizing Unit <dflip>.
    Related source file is G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd.
WARNING:Xst:1780 - Signal <temp2> is never used or assigned.
Unit <dflip> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 1-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1989 - Unit <dflip>: instances <u1>, <XLXI_6> of unit <dflipflop> are equivalent, second instance is removed

Optimizing unit <dflip> ...
Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dflip, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                       1  out of    768     0%  
 Number of Slice Flip Flops:             1  out of   1536     0%  
 Number of 4 input LUTs:                 1  out of   1536     0%  
 Number of bonded IOBs:                  2  out of    124     1%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 1.746ns (Maximum Frequency: 572.738MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.910ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.
ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 84. Index size for dimension 1 of ain is not 4.
ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 84. Index size for dimension 1 of bin is not 4.
ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 89. Index size for dimension 1 of stemp is not 2.
--> 

Total memory usage is 49400 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.
ERROR:HDLParsers:850 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 84. Formal port a2 does not exist in Component 'fbitaddr'.
ERROR:HDLParsers:850 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 84. Formal port b2 does not exist in Component 'fbitaddr'.
ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 89. Index size for dimension 1 of stemp is not 2.
--> 

Total memory usage is 49400 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd Line 30. Type of a is incompatible with type of a4.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd Line 30. Type of b is incompatible with type of b4.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd Line 33. Type of a is incompatible with type of a4.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd Line 33. Type of b is incompatible with type of b4.
--> 

Total memory usage is 46328 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.
Entity <fbitaddr> (Architecture <behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.
ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 89. Index size for dimension 1 of stemp is not 2.
--> 

Total memory usage is 49400 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.