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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.Entity <fulladdr> (Architecture <Behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.Entity <dflipflop> (Architecture <Behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.Entity <invtr> (Architecture <Behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.Entity <buff> (Architecture <Behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/testcnt.vhd in Library work.Entity <testcnt> (Architecture <Behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.Entity <dflip> (Architecture <BEHAVIORAL>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.Entity <fbitaddr> (Architecture <Behavioral>) compiled.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd in Library work.ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 84. Index size for dimension 1 of ain is not 4.ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 84. Index size for dimension 1 of bin is not 4.ERROR:HDLParsers:837 - G:/vijay_FPGA_LAB/alu_2bit/alu_2bit.vhd Line 89. Index size for dimension 1 of stemp is not 2.--> Total memory usage is 49400 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <fulladdr> (Architecture <behavioral>).Entity <fulladdr> analyzed. Unit <fulladdr> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <fulladdr>. Related source file is G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd.Unit <fulladdr> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <fulladdr> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block fulladdr, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 1 out of 768 0% Number of 4 input LUTs: 2 out of 1536 0% Number of bonded IOBs: 5 out of 124 4% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.103ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd in Library work.Architecture behavioral of Entity fulladdr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd in Library work.Entity <fbitaddr> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <fbitaddr> (Architecture <behavioral>).Entity <fbitaddr> analyzed. Unit <fbitaddr> generated.Analyzing Entity <fulladdr> (Architecture <behavioral>).Entity <fulladdr> analyzed. Unit <fulladdr> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <fulladdr>. Related source file is G:/vijay_FPGA_LAB/alu_2bit/fulladder.vhd.Unit <fulladdr> synthesized.Synthesizing Unit <fbitaddr>. Related source file is G:/vijay_FPGA_LAB/alu_2bit/fbitaddr.vhd.WARNING:Xst:1306 - Output <s4<3:2>> is never assigned.WARNING:Xst:1780 - Signal <c3> is never used or assigned.WARNING:Xst:1780 - Signal <c4> is never used or assigned.Unit <fbitaddr> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <fbitaddr> ...Optimizing unit <fulladdr> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block fbitaddr, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 2 out of 768 0% Number of 4 input LUTs: 4 out of 1536 0% Number of bonded IOBs: 8 out of 124 6% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 8.047ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.Entity <buff> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <buff> (Architecture <behavioral>).Entity <buff> analyzed. Unit <buff> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <buff>. Related source file is G:/vijay_FPGA_LAB/alu_2bit/buff.vhd.Unit <buff> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <buff> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block buff, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of bonded IOBs: 4 out of 124 3% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 6.159ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflipflop.vhd in Library work.Architecture behavioral of Entity dflipflop is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/invtr.vhd in Library work.Architecture behavioral of Entity invtr is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/buff.vhd in Library work.Architecture behavioral of Entity buff is up to date.Compiling vhdl file G:/vijay_FPGA_LAB/alu_2bit/dflip.vhd in Library work.Entity <dflip> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *⌨️ 快捷键说明
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