coregen.log

来自「this programs gives the fuctionality of 」· LOG 代码 · 共 22 行

# Xilinx CORE Generator 6.3i
# User = administrator
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\ACS\ACS_CD_SFW\cpld_fpga_sfw\VHDL_LAB_6_SEM_E&E_POLY\FPGA_PROGRAMS\FPGA_SW_PROGRAMS\1bit_add\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\ACS\ACS_CD_SFW\cpld_fpga_sfw\VHDL_LAB_6_SEM_E&E_POLY\FPGA_PROGRAMS\FPGA_SW_PROGRAMS\1bit_add
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=F:\ACS\ACS_CD_SFW\cpld_fpga_sfw\VHDL_LAB_6_SEM_E&E_POLY\FPGA_PROGRAMS\FPGA_SW_PROGRAMS\1bit_add
SETPROJECT .
Set current Project to F:\ACS\ACS_CD_SFW\cpld_fpga_sfw\VHDL_LAB_6_SEM_E&E_POLY\FPGA_PROGRAMS\FPGA_SW_PROGRAMS\1bit_add
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1028
XIPCPJSENDCORES spartan3