bit_add.vhd

来自「this programs gives the fuctionality of 」· VHDL 代码 · 共 41 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bit_add is
port(	cin	:in std_logic;
		a	:in std_logic;
		cout	:out std_logic;
		s	:out std_logic);	--carry out put 	
end bit_add;

architecture Behavioral of bit_add is

begin
		process(cin, a)
	begin
		if cin='1' then 
			if a='1' then 
				s<='1';
				cout<='0';
			else 
				s<='0';
				cout<='1';
			end if;
		else
			if a='1' then 
				s<='0';
				cout<='1';
			else
				s<='0';
				cout<='0';
			end if;
		end if;
	end process;
end Behavioral;