bit_add.par

this programs gives the fuctionality of 1 bit adder

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

P4::  Sat Mar 25 16:51:25 2006


E:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 bit_add_map.ncd
bit_add.ncd bit_add.pcf 


Constraints file: bit_add.pcf

Loading device database for application Par from file "bit_add_map.ncd".
   "bit_add" is an NCD, version 2.38, device xc3s50, package pq208, speed -4
Loading device for application Par from file '3s50.nph' in environment
E:/Xilinx.
Device speed data version:  ADVANCED 1.32 2004-06-25.


Resolved that IOB <cin> must be placed at site P27.
Resolved that IOB <s> must be placed at site P26.
Resolved that IOB <cout> must be placed at site P20.
Resolved that IOB <a> must be placed at site P21.


Device utilization summary:

   Number of External IOBs             4 out of 124     3%
      Number of LOCed External IOBs    4 out of 4     100%

   Number of Slices                    1 out of 768     1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989689) REAL time: 2 secs 

Phase 3.8
.
Phase 3.8 (Checksum:98989b) REAL time: 2 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 2 secs 

Writing design to file bit_add.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 6 unrouted;       REAL time: 2 secs 

Phase 2: 6 unrouted;       REAL time: 2 secs 

Phase 3: 0 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 44


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.418
   The MAXIMUM PIN DELAY IS:                               0.539
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.121

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           6           0           0           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  49 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file bit_add.ncd.


PAR done.