bit_add_map.vhd

this programs gives the fuctionality of 1 bit adder

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf bit_add.pcf -ngm bit_add.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim bit_add_map.ncd bit_add_map.vhd 
-- Input file    : bit_add_map.ncd
-- Output file   : bit_add_map.vhd
-- Design name   : bit_add
-- # of Entities : 1
-- Xilinx        : E:/Xilinx
-- Device        : 3s50pq208-4 (ADVANCED 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity bit_add is
  port (
    s : out STD_LOGIC; 
    cout : out STD_LOGIC; 
    cin : in STD_LOGIC := 'X'; 
    a : in STD_LOGIC := 'X' 
  );
end bit_add;

architecture Structure of bit_add is
  signal cin_IBUF : STD_LOGIC; 
  signal s_OBUF : STD_LOGIC; 
  signal cout_OBUF : STD_LOGIC; 
  signal a_IBUF : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal cin_INBUF : STD_LOGIC; 
  signal s_ENABLE : STD_LOGIC; 
  signal s_GTS_OR_T : STD_LOGIC; 
  signal s_O : STD_LOGIC; 
  signal cout_ENABLE : STD_LOGIC; 
  signal cout_GTS_OR_T : STD_LOGIC; 
  signal cout_O : STD_LOGIC; 
  signal a_INBUF : STD_LOGIC; 
  signal cout_OBUF_F : STD_LOGIC; 
  signal cout_OBUF_G : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
begin
  cin_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cin,
      O => cin_INBUF
    );
  s_OBUF_1 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => s_O,
      CTL => s_ENABLE,
      O => s
    );
  s_ENABLEINV : X_INV
    port map (
      I => s_GTS_OR_T,
      O => s_ENABLE
    );
  s_GTS_OR_T_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => s_GTS_OR_T
    );
  cout_OBUF_3 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cout_O,
      CTL => cout_ENABLE,
      O => cout
    );
  cout_ENABLEINV : X_INV
    port map (
      I => cout_GTS_OR_T,
      O => cout_ENABLE
    );
  cout_GTS_OR_T_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => cout_GTS_OR_T
    );
  a_IBUF_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a,
      O => a_INBUF
    );
  Q_n00021 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => a_IBUF,
      ADR1 => cin_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => cout_OBUF_G
    );
  cout_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cout_OBUF_F,
      O => cout_OBUF
    );
  cout_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cout_OBUF_G,
      O => s_OBUF
    );
  cout1 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => a_IBUF,
      ADR1 => cin_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => cout_OBUF_F
    );
  cin_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cin_INBUF,
      O => cin_IBUF
    );
  s_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => s_OBUF,
      O => s_O
    );
  cout_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => cout_OBUF,
      O => cout_O
    );
  a_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => a_INBUF,
      O => a_IBUF
    );
  NlwBlock_bit_add_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;