a linear feedback shift register is a sequential shift register with combinational logic that causes it to pseudo-randomly cycle through a sequence of binary values.mht

detals about linear feedback shift register

    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>0,21</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>23</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>8388607</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>4,22</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>24</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>16777215</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>0,2,3,23</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>25</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>33554431</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>2,24</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>26</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>67108863</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>0,1,5,25</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>27</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>134217727</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>0,1,4,26</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>28</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>268435455</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>2,27</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>29</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>536870911</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>1,28</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>30</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>1073741823</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>0.3,5,29</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>31</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>2147483647</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>2,30</FONT></P></TD></TR>
  <TR>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>32</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>4294967295</FONT></P></TD>
    <TD vAlign=3Dtop width=3D"33%"><FONT size=3D5>
      <P>1,5,6,31</FONT></P></TD></TR></TBODY></TABLE>
<P>Optimum Tap Points for Maximal Length Sequences</P><FONT size=3D5>
<P>&nbsp;</P><B>
<P>VHDL Code Usage - LFSR_Generic.vhd&nbsp;</P></B>
<P>&nbsp;</P>
<P>The implemented LFSR is coded for maximal length (2<SUP>N</SUP>-1), =
where N=20
is the number of bits in the LFSR. The VHDL entity can be instantiated =
with an=20
LFSR bit width of 2 to 32. </P>
<P>&nbsp;</P>
<P>The parallel "seed" input port (same length as the bit width) can be =
used to=20
start the LFSR sequence at a certain position in the pseudo-random =
sequence.=20
Assertion of the Active High "Load" signal at the rising edge of a clock =
will=20
load the seed value into the LFSR. &nbsp;</P>
<P>&nbsp;</P>
<P>Before the LFSR is used for the first time, the Active Low "Reset" =
must first=20
be asserted to initialize the Taps lookup table. One should ensure that =
"Load"=20
and "Reset" are not asserted at the same time or else undetermined =
behavior will=20
result. </P>
<P>&nbsp;</P>
<P>The LFSR outputs pseudo-random sequences in both serial and parallel =
format=20
for extra flexibility.</P>
<P>&nbsp;</P>
<P>The VHDL code for the LFSR as well as a component instantiation =
example are=20
provided.</P>
<P>&nbsp;</P><B>
<P>VHDL Testing</P></B>
<P>&nbsp;</P>
<P>Our group has tested this code in MAX+plus II. If you attempt to use =
this=20
code and it does not work, please email Raymond Sung</P>
<P>&nbsp;</P>
<H2>VHDL Code</H2><BR>
<P><A=20
href=3D"http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/Dr=
ivers_Ed/lfsr_generic.vhd">lfsr_generic.vhd</A></P>
<P><A=20
href=3D"http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/Dr=
ivers_Ed/lfsr_pkg.vhd">lfsr_pkg.vhd</A></P>
<P><A=20
href=3D"http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/Dr=
ivers_Ed/lfsr_generic_test.vhd">lfsr_generic_test.vhd</A></P><BR>&nbsp;=20

<P>Authors: Raymond Sung, Andrew Sung, Patrick Chan, Jason=20
Mah</P></FONT></BODY></HTML>

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