pci.h

newos is new operation system

/*
** Copyright 2001-2003, Travis Geiselbrecht. All rights reserved.
** Distributed under the terms of the NewOS License.
*/
/* Portions Copyright: */
//------------------------------------------------------------------------------
//  Copyright (c) 2001-2002, OpenBeOS
//
//  Permission is hereby granted, free of charge, to any person obtaining a
//  copy of this software and associated documentation files (the "Software"),
//  to deal in the Software without restriction, including without limitation
//  the rights to use, copy, modify, merge, publish, distribute, sublicense,
//  and/or sell copies of the Software, and to permit persons to whom the
//  Software is furnished to do so, subject to the following conditions:
//
//  The above copyright notice and this permission notice shall be included in
//  all copies or substantial portions of the Software.
//
//  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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//  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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//------------------------------------------------------------------------------

#ifndef _PCI_BUS_H
#define _PCI_BUS_H

#include <boot/stage2.h>

#define PCI_BUS_MODULE_NAME "bus_managers/pci/v1"

/* stolen from OpenBEOS sources */

typedef struct pci_info {
	ushort	vendor_id;				/* vendor id */
	ushort	device_id;				/* device id */
	uchar	bus;					/* bus number */
	uchar	device;					/* device number on bus */
	uchar	function;				/* function number in device */
	uchar	revision;				/* revision id */
	uchar	class_api;				/* specific register interface type */
	uchar	class_sub;				/* specific device function */
	uchar	class_base;				/* device type (display vs network, etc) */
	uchar	line_size;				/* cache line size in 32 bit words */
	uchar	latency;				/* latency timer */
	uchar	header_type;			/* header type */
	uchar	bist;					/* built-in self-test */
	uchar	reserved;				/* filler, for alignment */
	union {
		struct {
			ulong	cardbus_cis;			/* CardBus CIS pointer */
			ushort	subsystem_id;			/* subsystem (add-in card) id */
			ushort	subsystem_vendor_id;	/* subsystem (add-in card) vendor id */
			ulong	rom_base;				/* rom base address, viewed from host */
			ulong	rom_base_pci;			/* rom base addr, viewed from pci */
			ulong	rom_size;				/* rom size */
			ulong	base_registers[6];		/* base registers, viewed from host */
			ulong	base_registers_pci[6];	/* base registers, viewed from pci */
			ulong	base_register_sizes[6];	/* size of what base regs point to */
			uchar	base_register_flags[6];	/* flags from base address fields */
			uchar	interrupt_line;			/* interrupt line */
			uchar	interrupt_pin;			/* interrupt pin */
			uchar	min_grant;				/* burst period @ 33 Mhz */
			uchar	max_latency;			/* how often PCI access needed */
		} h0;
		struct {
			ulong	base_registers[2];		/* base registers, viewed from host */
			ulong	base_registers_pci[2];	/* base registers, viewed from pci */
			ulong	base_register_sizes[2];	/* size of what base regs point to */
			uchar	base_register_flags[2];	/* flags from base address fields */
			uchar	primary_bus;
			uchar	secondary_bus;
			uchar	subordinate_bus;
			uchar	secondary_latency;
			uchar	io_base;
			uchar	io_limit;
			ushort	secondary_status;
			ushort	memory_base;
			ushort	memory_limit;
			ushort  prefetchable_memory_base;
			ushort  prefetchable_memory_limit;
			ulong	prefetchable_memory_base_upper32;
			ulong	prefetchable_memory_limit_upper32;
			ushort	io_base_upper16;
			ushort	io_limit_upper16;
			ulong	rom_base;				/* rom base address, viewed from host */
			ulong	rom_base_pci;			/* rom base addr, viewed from pci */
			uchar	interrupt_line;			/* interrupt line */
			uchar	interrupt_pin;			/* interrupt pin */
			ushort	bridge_control;
			ushort	subsystem_id;			/* subsystem (add-in card) id */
			ushort	subsystem_vendor_id;	/* subsystem (add-in card) vendor id */
		} h1;
		struct {
			ushort	subsystem_id;			/* subsystem (add-in card) id */
			ushort	subsystem_vendor_id;	/* subsystem (add-in card) vendor id */
		} h2;
	} u;
} pci_info;

struct pci_module_hooks {
	uint8			(*read_io_8) (int mapped_io_addr);
	void			(*write_io_8) (int mapped_io_addr, uint8 value);
	uint16			(*read_io_16) (int mapped_io_addr);
	void			(*write_io_16) (int mapped_io_addr, uint16 value);
	uint32			(*read_io_32) (int mapped_io_addr);
	void			(*write_io_32) (int mapped_io_addr, uint32 value);

	long			(*get_nth_pci_info) (
						long		index,	/* index into pci device table */
						pci_info 	*info	/* caller-supplied buffer for info */
					);
	uint32			(*read_pci_config) (
						uchar	bus,		/* bus number */
						uchar	device,		/* device # on bus */
						uchar	function,	/* function # in device */
						uchar	offset,		/* offset in configuration space */
						uchar	size		/* # bytes to read (1, 2 or 4) */
					);
	void			(*write_pci_config) (
						uchar	bus,		/* bus number */
						uchar	device,		/* device # on bus */
						uchar	function,	/* function # in device */
						uchar	offset,		/* offset in configuration space */
						uchar	size,		/* # bytes to write (1, 2 or 4) */
						uint32	value		/* value to write */
					);

	void *			(*ram_address) (const void *physical_address_in_system_memory);
};

typedef struct pci_module_hooks pci_module_hooks;

/* defines */

/* ---
	offsets in PCI configuration space to the elements of the predefined
	header common to all header types
--- */

#define PCI_vendor_id			0x00		/* (2 byte) vendor id */
#define PCI_device_id			0x02		/* (2 byte) device id */
#define PCI_command				0x04		/* (2 byte) command */
#define PCI_status				0x06		/* (2 byte) status */
#define PCI_revision			0x08		/* (1 byte) revision id */
#define PCI_class_api			0x09		/* (1 byte) specific register interface type */
#define PCI_class_sub			0x0a		/* (1 byte) specific device function */
#define PCI_class_base			0x0b		/* (1 byte) device type (display vs network, etc) */
#define PCI_line_size			0x0c		/* (1 byte) cache line size in 32 bit words */
#define PCI_latency				0x0d		/* (1 byte) latency timer */
#define PCI_header_type			0x0e		/* (1 byte) header type */
#define PCI_bist				0x0f		/* (1 byte) built-in self-test */



/* ---
	offsets in PCI configuration space to the elements of the predefined
	header common to header types 0x00 and 0x01
--- */
#define PCI_base_registers		0x10		/* base registers (size varies) */
#define PCI_interrupt_line		0x3c		/* (1 byte) interrupt line */
#define PCI_interrupt_pin		0x3d		/* (1 byte) interrupt pin */



/* ---
	offsets in PCI configuration space to the elements of header type 0x00
--- */

#define PCI_cardbus_cis			0x28		/* (4 bytes) CardBus CIS (Card Information Structure) pointer (see PCMCIA v2.10 Spec) */
#define PCI_subsystem_vendor_id	0x2c		/* (2 bytes) subsystem (add-in card) vendor id */
#define PCI_subsystem_id		0x2e		/* (2 bytes) subsystem (add-in card) id */
#define PCI_rom_base			0x30		/* (4 bytes) expansion rom base address */
#define PCI_capabilities_ptr    0x34        /* (1 byte) pointer to the start of the capabilities list */
#define PCI_min_grant			0x3e		/* (1 byte) burst period @ 33 Mhz */
#define PCI_max_latency			0x3f		/* (1 byte) how often PCI access needed */


/* ---
	offsets in PCI configuration space to the elements of header type 0x01 (PCI-to-PCI bridge)
--- */

#define PCI_primary_bus								0x18 /* (1 byte) */
#define PCI_secondary_bus							0x19 /* (1 byte) */
#define PCI_subordinate_bus							0x1A /* (1 byte) */
#define PCI_secondary_latency						0x1B /* (1 byte) latency of secondary bus */
#define PCI_io_base									0x1C /* (1 byte) io base address register for 2ndry bus*/
#define PCI_io_limit								0x1D /* (1 byte) */
#define PCI_secondary_status						0x1E /* (2 bytes) */
#define PCI_memory_base								0x20 /* (2 bytes) */
#define PCI_memory_limit							0x22 /* (2 bytes) */
#define PCI_prefetchable_memory_base				0x24 /* (2 bytes) */
#define PCI_prefetchable_memory_limit				0x26 /* (2 bytes) */
#define PCI_prefetchable_memory_base_upper32		0x28
#define PCI_prefetchable_memory_limit_upper32		0x2C
#define PCI_io_base_upper16							0x30 /* (2 bytes) */
#define PCI_io_limit_upper16						0x32 /* (2 bytes) */
#define PCI_sub_vendor_id_1                         0x34 /* (2 bytes) */
#define PCI_sub_device_id_1                         0x36 /* (2 bytes) */
#define PCI_bridge_rom_base							0x38
#define PCI_bridge_control							0x3E /* (1 byte) */


/* PCI type 2 header offsets */
#define PCI_capabilities_ptr_2                      0x14 /* (1 byte) */
#define PCI_secondary_status_2                      0x16 /* (2 bytes) */
#define PCI_primary_bus_2							0x18 /* (1 byte) */
#define PCI_secondary_bus_2							0x19 /* (1 byte) */
#define PCI_subordinate_bus_2						0x1A /* (1 byte) */
#define PCI_secondary_latency_2                     0x1B /* (1 byte) latency of secondary bus */
#define PCI_memory_base0_2                          0x1C /* (4 bytes) */
#define PCI_memory_limit0_2                         0x20 /* (4 bytes) */
#define PCI_memory_base1_2                          0x24 /* (4 bytes) */
#define PCI_memory_limit1_2                         0x28 /* (4 bytes) */
#define PCI_io_base0_2                              0x2c /* (4 bytes) */
#define PCI_io_limit0_2                             0x30 /* (4 bytes) */
#define PCI_io_base1_2                              0x34 /* (4 bytes) */
#define PCI_io_limit1_2                             0x38 /* (4 bytes) */
#define PCI_bridge_control_2                        0x3E /* (1 byte) */

#define PCI_sub_vendor_id_2                         0x40 /* (2 bytes) */
#define PCI_sub_device_id_2                         0x42 /* (2 bytes) */

#define PCI_card_interface_2                        0x44 /* ?? */

/* ---
	values for the class_base field in the common header
--- */

#define PCI_early					0x00	/* built before class codes defined */
#define PCI_mass_storage			0x01	/* mass storage_controller */
#define PCI_network					0x02	/* network controller */
#define PCI_display					0x03	/* display controller */
#define PCI_multimedia				0x04	/* multimedia device */
#define PCI_memory					0x05	/* memory controller */
#define PCI_bridge					0x06	/* bridge controller */
#define PCI_simple_communications	0x07	/* simple communications controller */
#define PCI_base_peripheral			0x08	/* base system peripherals */
#define PCI_input					0x09	/* input devices */
#define PCI_docking_station			0x0a	/* docking stations */
#define PCI_processor				0x0b	/* processors */
#define PCI_serial_bus				0x0c	/* serial_bus_controller */

#define PCI_undefined				0xFF	/* not in any defined class */


/* ---
	values for the class_sub field for class_base = 0x00 (built before
	class codes were defined)
--- */

#define PCI_early_not_vga	0x00			/* all except vga */
#define PCI_early_vga		0x01			/* vga devices */


/* ---
	values for the class_sub field for class_base = 0x01 (mass storage)
--- */

#define PCI_scsi			0x00			/* SCSI controller */
#define PCI_ide				0x01			/* IDE controller */
#define PCI_floppy			0x02			/* floppy disk controller */
#define PCI_ipi				0x03			/* IPI bus controller */
#define PCI_raid			0x04			/* RAID controller */
#define PCI_mass_storage_other 0x80			/* other mass storage controller */


/* ---
	values for the class_sub field for class_base = 0x02 (network)
--- */

#define PCI_ethernet		0x00			/* Ethernet controller */
#define PCI_token_ring		0x01			/* Token Ring controller */
#define PCI_fddi			0x02			/* FDDI controller */
#define PCI_atm				0x03			/* ATM controller */
#define PCI_isdn            0x04            /* ISDN controller */
#define PCI_network_other	0x80			/* other network controller */


/* ---
	values for the class_sub field for class_base = 0x03 (display)
--- */

#define PCI_vga				0x00			/* VGA controller */
#define PCI_xga				0x01			/* XGA controller */
#define PCI_3d              0x02            /* £d controller */
#define PCI_display_other	0x80			/* other display controller */


/* ---
	values for the class_sub field for class_base = 0x04 (multimedia device)
--- */

#define PCI_video			 0x00			/* video */
#define PCI_audio			 0x01			/* audio */
#define PCI_telephony        0x02           /* computer telephony device */
#define PCI_multimedia_other 0x80			/* other multimedia device */