ctlreg.h

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/*
 * [4m] Registers and bits in the SPARC Reference MMU (ASI_SRMMU).
 */
#define SRMMU_PCR	0x00000000	/* Processor control register */
#define SRMMU_CXTPTR	0x00000100	/* Context table pointer register */
#define SRMMU_CXR	0x00000200	/* Context register */
#define SRMMU_SFSR	0x00000300	/* Synchronous fault status reg */
#define SRMMU_SFAR	0x00000400	/* Synchronous fault address reg */
#define SRMMU_AFSR	0x00000500	/* Asynchronous fault status reg (HS)*/
#define SRMMU_AFAR	0x00000600	/* Asynchronous fault address reg (HS)*/
#define SRMMU_PCFG	0x00000600	/* Processor configuration reg (TURBO)*/
#define SRMMU_TLBCTRL	0x00001000	/* TLB replacement control reg */


/*
 * [4m] Bits in SRMMU control register. One set per module.
 */
#define VIKING_PCR_ME	0x00000001	/* MMU Enable */
#define VIKING_PCR_NF	0x00000002	/* Fault inhibit bit */
#define VIKING_PCR_PSO	0x00000080	/* Partial Store Ordering enable */
#define VIKING_PCR_DCE	0x00000100	/* Data cache enable bit */
#define VIKING_PCR_ICE	0x00000200	/* SuperSPARC instr. cache enable */
#define VIKING_PCR_SB	0x00000400	/* Store buffer enable bit */
#define VIKING_PCR_MB	0x00000800	/* MBus mode: 0=MXCC, 1=no MXCC */
#define VIKING_PCR_PE	0x00001000	/* Enable memory parity checking */
#define VIKING_PCR_BM	0x00002000	/* 1 iff booting */
#define VIKING_PCR_SE	0x00004000	/* Coherent bus snoop enable */
#define VIKING_PCR_AC	0x00008000	/* 1=cache non-MMU accesses */
#define	VIKING_PCR_TC	0x00010000	/* 1=cache table walks */

#define HYPERSPARC_PCR_ME	0x00000001	/* MMU Enable */
#define HYPERSPARC_PCR_NF	0x00000002	/* Fault inhibit bit */
#define HYPERSPARC_PCR_CE	0x00000100	/* Cache enable bit */
#define HYPERSPARC_PCR_CM	0x00000400	/* Cache mode: 1=write-back */
#define	HYPERSPARC_PCR_MR	0x00000800	/* Memory reflection: 1 = on */
#define HYPERSPARC_PCR_CS	0x00001000	/* cache size: 1=256k, 0=128k */
#define HYPERSPARC_PCR_C	0x00002000	/* enable cache when MMU off */
#define HYPERSPARC_PCR_BM	0x00004000	/* 1 iff booting */
#define HYPERSPARC_PCR_MID	0x00078000	/* MBus module ID MID<3:0> */
#define HYPERSPARC_PCR_WBE	0x00080000	/* Write buffer enable */
#define HYPERSPARC_PCR_SE	0x00100000	/* Coherent bus snoop enable */
#define HYPERSPARC_PCR_CWR	0x00200000	/* Cache wrap enable */

#define CYPRESS_PCR_ME	0x00000001	/* MMU Enable */
#define CYPRESS_PCR_NF	0x00000002	/* Fault inhibit bit */
#define CYPRESS_PCR_CE	0x00000100	/* Cache enable bit */
#define CYPRESS_PCR_CL	0x00000200	/* Cache Lock (604 only) */
#define CYPRESS_PCR_CM	0x00000400	/* Cache mode: 1=write-back */
#define	CYPRESS_PCR_MR	0x00000800	/* Memory reflection: 1=on (605 only) */
#define CYPRESS_PCR_C	0x00002000	/* enable cache when MMU off */
#define CYPRESS_PCR_BM	0x00004000	/* 1 iff booting */
#define CYPRESS_PCR_MID	0x00078000	/* MBus module ID MID<3:0> (605 only) */
#define CYPRESS_PCR_MV	0x00080000	/* Multichip Valid */
#define CYPRESS_PCR_MCM	0x00300000	/* Multichip Mask */
#define CYPRESS_PCR_MCA	0x00c00000	/* Multichip Address */

#define MS1_PCR_ME	0x00000001	/* MMU Enable */
#define MS1_PCR_NF	0x00000002	/* Fault inhibit bit */
#define MS1_PCR_DCE	0x00000100	/* Data cache enable */
#define MS1_PCR_ICE	0x00000200	/* Instruction cache enable */
#define MS1_PCR_RC	0x00000c00	/* DRAM Refresh control */
#define MS1_PCR_PE	0x00001000	/* Enable memory parity checking */
#define MS1_PCR_BM	0x00004000	/* 1 iff booting */
#define MS1_PCR_AC	0x00008000	/* 1=cache if ME==0 (and [ID]CE on) */
#define	MS1_PCR_ID	0x00010000	/* 1=disable ITBR */
#define	MS1_PCR_PC	0x00020000	/* Parity control: 0=even,1=odd */
#define	MS1_PCR_MV	0x00100000	/* Memory data View (diag) */
#define	MS1_PCR_DV	0x00200000	/* Data View (diag) */
#define	MS1_PCR_AV	0x00400000	/* Address View (diag) */
#define	MS1_PCR_STW	0x00800000	/* Software Tablewalk enable */

#define SWIFT_PCR_ME	0x00000001	/* MMU Enable */
#define SWIFT_PCR_NF	0x00000002	/* Fault inhibit bit */
#define SWIFT_PCR_DCE	0x00000100	/* Data cache enable */
#define SWIFT_PCR_ICE	0x00000200	/* Instruction cache enable */
#define SWIFT_PCR_RC	0x00003c00	/* DRAM Refresh control */
#define SWIFT_PCR_BM	0x00004000	/* 1 iff booting */
#define SWIFT_PCR_AC	0x00008000	/* 1=cache if ME=0 (and [ID]CE on) */
#define	SWIFT_PCR_PA	0x00010000	/* TCX/SX control */
#define	SWIFT_PCR_PC	0x00020000	/* Parity control: 0=even,1=odd */
#define SWIFT_PCR_PE	0x00040000	/* Enable memory parity checking */
#define	SWIFT_PCR_PMC	0x00180000	/* Page mode control */
#define	SWIFT_PCR_BF	0x00200000	/* Branch Folding */
#define	SWIFT_PCR_WP	0x00400000	/* Watch point enable */
#define	SWIFT_PCR_STW	0x00800000	/* Software Tablewalk enable */

#define TURBOSPARC_PCR_ME	0x00000001	/* MMU Enable */
#define TURBOSPARC_PCR_NF	0x00000002	/* Fault inhibit bit */
#define TURBOSPARC_PCR_ICS	0x00000004	/* I-cache snoop enable */
#define TURBOSPARC_PCR_PSO	0x00000008	/* Partial Store order (ro!) */
#define TURBOSPARC_PCR_DCE	0x00000100	/* Data cache enable */
#define TURBOSPARC_PCR_ICE	0x00000200	/* Instruction cache enable */
#define TURBOSPARC_PCR_RC	0x00003c00	/* DRAM Refresh control */
#define TURBOSPARC_PCR_BM	0x00004000	/* 1 iff booting */
#define	TURBOSPARC_PCR_PC	0x00020000	/* Parity ctrl: 0=even,1=odd */
#define TURBOSPARC_PCR_PE	0x00040000	/* Enable parity checking */
#define	TURBOSPARC_PCR_PMC	0x00180000	/* Page mode control */

/* The Turbosparc's Processor Configuration Register */
#define	TURBOSPARC_PCFG_SCC	0x00000007	/* e-cache config */
#define	TURBOSPARC_PCFG_SE	0x00000008	/* e-cache enable */
#define	TURBOSPARC_PCFG_US2	0x00000010	/* microsparc II compat */
#define	TURBOSPARC_PCFG_WT	0x00000020	/* write-through enable */
#define	TURBOSPARC_PCFG_SBC	0x000000c0	/* SBus Clock */
#define	TURBOSPARC_PCFG_WS	0x03800000	/* DRAM wait states */
#define	TURBOSPARC_PCFG_RAH	0x0c000000	/* DRAM Row Address Hold */
#define	TURBOSPARC_PCFG_AXC	0x30000000	/* AFX Clock */
#define	TURBOSPARC_PCFG_SNP	0x40000000	/* DVMA Snoop enable */
#define	TURBOSPARC_PCFG_IOCLK	0x80000000	/* I/O clock ratio */


/* Implementation and Version fields are common to all modules */
#define SRMMU_PCR_VER	0x0f000000	/* Version of MMU implementation */
#define SRMMU_PCR_IMPL	0xf0000000	/* Implementation number of MMU */


/* [4m] Bits in the Synchronous Fault Status Register */
#define SFSR_EM		0x00020000	/* Error mode watchdog reset occurred */
#define SFSR_CS		0x00010000	/* Control Space error */
#define SFSR_PERR	0x00006000	/* Parity error code */
#define SFSR_SB		0x00008000	/* SS: Store Buffer Error */
#define SFSR_P		0x00004000	/* SS: Parity error */
#define SFSR_UC		0x00001000	/* Uncorrectable error */
#define SFSR_TO		0x00000800	/* S-Bus timeout */
#define SFSR_BE		0x00000400	/* S-Bus bus error */
#define SFSR_LVL	0x00000300	/* Pagetable level causing the fault */
#define SFSR_AT		0x000000e0	/* Access type */
#define SFSR_FT		0x0000001c	/* Fault type */
#define SFSR_FAV	0x00000002	/* Fault Address is valid */
#define SFSR_OW		0x00000001	/* Overwritten with new fault */

#define	SFSR_BITS \
"\20\21CSERR\17PARITY\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\2FAV\1OW"

/* [4m] Synchronous Fault Types */
#define SFSR_FT_NONE		(0 << 2) 	/* no fault */
#define SFSR_FT_INVADDR		(1 << 2)	/* invalid address fault */
#define SFSR_FT_PROTERR		(2 << 2)	/* protection fault */
#define SFSR_FT_PRIVERR		(3 << 2)	/* privelege violation */
#define SFSR_FT_TRANSERR	(4 << 2)	/* translation fault */
#define SFSR_FT_BUSERR		(5 << 2)	/* access bus error */
#define SFSR_FT_INTERR		(6 << 2)	/* internal error */
#define SFSR_FT_RESERVED	(7 << 2)	/* reserved */

/* [4m] Synchronous Fault Access Types */
#define SFSR_AT_LDUDATA		(0 << 5)     	/* Load user data */
#define SFSR_AT_LDSDATA		(1 << 5)	/* Load supervisor data */
#define SFSR_AT_LDUTEXT		(2 << 5)	/* Load user text */
#define SFSR_AT_LDSTEXT		(3 << 5)	/* Load supervisor text */
#define SFSR_AT_STUDATA		(4 << 5)	/* Store user data */
#define SFSR_AT_STSDATA		(5 << 5) 	/* Store supervisor data */
#define SFSR_AT_STUTEXT		(6 << 5)	/* Store user text */
#define SFSR_AT_STSTEXT		(7 << 5)	/* Store supervisor text */
#define SFSR_AT_SUPERVISOR	(1 << 5)	/* Set iff supervisor */
#define SFSR_AT_TEXT		(2 << 5)	/* Set iff text */
#define SFSR_AT_STORE		(4 << 5)	/* Set iff store */

/* [4m] Synchronous Fault PT Levels */
#define SFSR_LVL_0		(0 << 8)	/* Context table entry */
#define SFSR_LVL_1		(1 << 8)	/* Region table entry */
#define SFSR_LVL_2		(2 << 8)	/* Segment table entry */
#define SFSR_LVL_3		(3 << 8)	/* Page table entry */

/* [4m] Asynchronous Fault Status Register bits */
#define AFSR_AFO	0x00000001	/* Async. fault occurred */
#define AFSR_AFA	0x000000f0	/* Bits <35:32> of faulting phys addr */
#define AFSR_AFA_RSHIFT	4		/* Shift to get AFA to bit 0 */
#define AFSR_AFA_LSHIFT	28		/* Shift to get AFA to bit 32 */
#define AFSR_BE		0x00000400	/* Bus error */
#define AFSR_TO		0x00000800	/* Bus timeout */
#define AFSR_UC		0x00001000	/* Uncorrectable error */
#define AFSR_SE		0x00002000	/* System error */

#define	AFSR_BITS	"\20\16SYSERR\15UNCORR\14TIMEOUT\13BUSERR\1AFO"

/* [4m] TLB Replacement Control Register bits */
#define TLBC_DISABLE	0x00000020	/* Disable replacement counter */
#define TLBC_RCNTMASK	0x0000001f	/* Replacement counter (0-31) */

/*
 * The Ross Hypersparc has an Instruction Cache Control Register (ICCR)
 * It contains an enable bit for the on-chip instruction cache and a bit
 * that controls whether a FLUSH instruction causes an Unimplemented
 * Flush Trap or just flushes the appropriate instruction cache line.
 * The ICCR register is implemented as Ancillary State register number 31.
 */
#define	HYPERSPARC_ICCR_ICE	1	/* Instruction cache enable */
#define	HYPERSPARC_ICCR_FTD	2	/* Unimpl. flush trap disable */
#define	HYPERSPARC_ASRNUM_ICCR	31	/* ICCR == ASR#31 */