📄 bdm.c
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/* bit 3 */
STX ,X /* drive BDM low */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
NOP /* wait 1 cycle */
/* bit 2 */
STX ,X /* drive BDM low */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
NOP /* wait 1 cycle */
/* bit 1 */
STX ,X /* drive BDM low */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
NOP /* wait 1 cycle */
/* bit 0 */
STX ,X /* drive BDM low */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
/* now get the bit values (last value is in X, previous 7 on stack) */
JMP rx_stack_decode
}
}
/* 3.38 - 4.48 MHz */
unsigned char bdm_rx5(void) {
#pragma NO_RETURN
asm {
LDA #BDM_DIR1_MASK+RESET_OUT_MASK /* contents of A will be driven to PTA in order to switch the driver off */
CLRX /* prepare HX to point to PTA */
CLRH
/* bit 7 (MSB) */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 6 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 5 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 4 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 3 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 2 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 1 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
PSHX /* store the value on the stack */
CLRX /* clear X again */
BIT ,X /* wait 2 cycles */
/* bit 0 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRN 0 /* wait 3 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
/* now get the bit values (last value is in X, previous 7 on stack) */
JMP rx_stack_decode
}
}
/* 2.7 - 3.9 MHz */
unsigned char bdm_rx6(void) {
asm {
LDA #BDM_DIR1_MASK+RESET_OUT_MASK /* contents of A will be driven to PTA in order to switch the driver off */
CLRX /* prepare HX to point to PTA */
CLRH
/* bit 7 (MSB) */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
BRSET 0,DDRA,0 /* wait 5 cycles */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 6 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle (5 cycles in total together with ROL) */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 5 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 4 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 3 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 2 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 1 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
CLRX /* clear X again */
BRN 0 /* wait 3 cycles */
/* bit 0 */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 more cycle */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
ROL i /* shift C into i (from the bottom) */
LDA i /* load the result into A */
}
}
/* 2.25 - 3.25 MHz */
unsigned char bdm_rx7(void) {
asm {
LDA #BDM_DIR1_MASK+RESET_OUT_MASK /* contents of A will be driven to PTA in order to switch the driver off */
MOV #8,j /* store number of iterations into j */
CLRH /* prepare H */
loop:
/* the following construction is a bit awkward cause by the fact that there is time for loop iteration in the middle of the routine, but not at its end... */
/* this is the end of bit processing, it is done 1 extra time before bit 7 (but that does not matter) */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
ROL i /* shift C into i (from the bottom) */
NOP /* wait 1 cycle (5 in total with ROL) */
CLRX /* clear X for HX to point to PTA */
/* here the bit begins */
STX ,X /* drive BDM low */
NOP /* wait 1 cycle */
STA ,X /* switch BDM to high impedance */
DEC j /* iterate the loop (this takes 7 cycles) */
BNE loop
/* finish processing of bit 0 (after exit from the loop) */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
ROL i /* shift C into i (from the bottom) */
LDA i /* load the result into A */
}
}
/* 1.8 - 2.6 MHz */
unsigned char bdm_rx8(void) {
asm {
LDA #BDM_DIR1_MASK+RESET_OUT_MASK /* contents of A will be driven to PTA in order to switch the driver off */
MOV #8,j /* store number of iterations into j */
CLRH /* prepare H */
loop:
CLRX /* clear X to point to PTA, CLRX has been moved to the beginning of the algorithm here to prevent its execution for the last bit */
STX ,X /* drive BDM low */
NOP /* wait 2 cycles, cannot use BIT here as it changes C */
NOP
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
BRSET 0,DDRA,0 /* wait 5 cycles (9 in total with ROL) */
LDX ,X /* load X with value on the PTA port (including BDM_IN) */
LSLX /* shift BDM_IN into C */
LSLX
DEC j /* iterate the loop (this takes 7 cycles) */
BNE loop
ROL i /* shift C into i (from the bottom) */
LDA i /* load the result into A */
}
}
/* 1.5 - 2.166 MHz */
unsigned char bdm_rx9(void) {
asm {
LDA #BDM_DIR1_MASK+RESET_OUT_MASK /* contents of A will be driven to PTA in order to switch the driver off */
MOV #8,j /* store number of iterations into j */
CLRH /* prepare H */
loop:
CLRX /* clear X to point to PTA, CLRX has been moved to the beginning of the algorithm here to prevent its execution for the last bit */
STX ,X /* drive BDM low */
NOP /* wait 2 cycles, cannot use BIT here as it changes C */
NOP
STA ,X /* switch BDM to high impedance */
ROL i /* shift C into i (from the bottom) */
BIT ,X /* wait 8 cycles (12 in total with ROL) */
BIT ,X
BIT ,X
BIT ,X
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